f2b33d794d
This patch moves InstCounterType and Waitcnt from Utils/AMDGPUBaseInfo.h to a more appropriate location, one directory up, in AMDGPUWaitcntUtils.h. We also need to move a few encoding and decoding functions that work on Waitcnt. Some of these called static functions defined in AMDGPUBaseInfo.cpp, like `unpackBits()`, so this patch introduced new functions in AMDGPUBaseInfo: `decodeLoadcnt()`, `decodeStorecnt()` and `decodeDscnt()` that do the necessary bit operations but don't operate on the Waitcnt class directly.
91 lines
2.7 KiB
C++
91 lines
2.7 KiB
C++
//===- AMDGPUWaitcntUtils.cpp ---------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUWaitcntUtils.h"
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#include "Utils/AMDGPUBaseInfo.h"
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namespace llvm::AMDGPU {
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iota_range<InstCounterType> inst_counter_types(InstCounterType MaxCounter) {
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return enum_seq(LOAD_CNT, MaxCounter);
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}
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StringLiteral getInstCounterName(InstCounterType T) {
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switch (T) {
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case LOAD_CNT:
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return "LOAD_CNT";
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case DS_CNT:
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return "DS_CNT";
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case EXP_CNT:
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return "EXP_CNT";
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case STORE_CNT:
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return "STORE_CNT";
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case SAMPLE_CNT:
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return "SAMPLE_CNT";
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case BVH_CNT:
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return "BVH_CNT";
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case KM_CNT:
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return "KM_CNT";
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case X_CNT:
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return "X_CNT";
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case ASYNC_CNT:
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return "ASYNC_CNT";
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case VA_VDST:
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return "VA_VDST";
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case VM_VSRC:
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return "VM_VSRC";
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case NUM_INST_CNTS:
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return "NUM_INST_CNTS";
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}
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llvm_unreachable("Unhandled InstCounterType");
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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void Waitcnt::dump() const { dbgs() << *this << '\n'; }
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#endif
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Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
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Waitcnt Decoded;
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Decoded.set(LOAD_CNT, decodeVmcnt(Version, Encoded));
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Decoded.set(EXP_CNT, decodeExpcnt(Version, Encoded));
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Decoded.set(DS_CNT, decodeLgkmcnt(Version, Encoded));
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return Decoded;
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}
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unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
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return encodeWaitcnt(Version, Decoded.get(LOAD_CNT), Decoded.get(EXP_CNT),
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Decoded.get(DS_CNT));
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}
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Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt) {
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Waitcnt Decoded;
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Decoded.set(LOAD_CNT, decodeLoadcnt(Version, LoadcntDscnt));
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Decoded.set(DS_CNT, decodeDscnt(Version, LoadcntDscnt));
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return Decoded;
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}
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Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt) {
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Waitcnt Decoded;
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Decoded.set(STORE_CNT, decodeStorecnt(Version, StorecntDscnt));
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Decoded.set(DS_CNT, decodeDscnt(Version, StorecntDscnt));
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return Decoded;
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}
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unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded) {
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return encodeLoadcntDscnt(Version, Decoded.get(LOAD_CNT),
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Decoded.get(DS_CNT));
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}
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unsigned encodeStorecntDscnt(const IsaVersion &Version,
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const Waitcnt &Decoded) {
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return encodeStorecntDscnt(Version, Decoded.get(STORE_CNT),
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Decoded.get(DS_CNT));
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}
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} // namespace llvm::AMDGPU
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