Vigneshwar Jayakumar dc94465807 [AMDGPU] Add readfirstlane for inline asm SGPR with VGPR input (#176330) ...

SIFixSGPRCopies was incorrectly handling inline assembly operands with
SGPR ("s") constraints when the value came from a memory load (which
produces a VGPR). The pass would fail to insert the necessary
v_readfirstlane instruction instead directly passes the vgpr value.
example:
  asm sideeffect buffer_load_dwordx4 $0, $1, $2, 0 =v,v,s,n
previously it generated:
buffer_load_dwordx4 v[0:3], v0, v[8:11] (but sgpr is expected), 0 offen

The fix adds readfirstlanes during lowering when there is a copy from
divergent register to SGPR.

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>

2026-04-30 12:45:20 -05:00

..

AsmParser

[AMDGPU][MC] update USER_SGPR_COUNT bits for GFX1250 (#192579)

2026-04-28 21:25:29 -07:00

Disassembler

[MC] Make MCContext::getAsmInfo return a reference. NFC (#194523)

2026-04-28 03:57:47 +00:00

MCA

…

MCTargetDesc

[AMDGPU][NFC] Remove redundant Args.size() assertions from AMDGPUMCExpr (#194488)

2026-04-28 09:27:22 -05:00

TargetInfo

…

Utils

[MC] Make MCContext::getAsmInfo return a reference. NFC (#194523)

2026-04-28 03:57:47 +00:00

AMDGPU.h

AMDGPU: Add NextUseAnalysis Pass (#178873)

2026-04-16 12:05:59 -05:00

AMDGPU.td

[AMDGPU] Enable real true16 on gfx1250 (#190452)

2026-04-15 10:42:52 -07:00

AMDGPUAliasAnalysis.cpp

…

AMDGPUAliasAnalysis.h

…

AMDGPUAlwaysInlinePass.cpp

…

AMDGPUAnnotateUniformValues.cpp

…

AMDGPUArgumentUsageInfo.cpp

…

AMDGPUArgumentUsageInfo.h

…

AMDGPUAsanInstrumentation.cpp

…

AMDGPUAsanInstrumentation.h

…

AMDGPUAsmPrinter.cpp

[AMDGPU][MC] update USER_SGPR_COUNT bits for GFX1250 (#192579)

2026-04-28 21:25:29 -07:00

AMDGPUAsmPrinter.h

[AMDGPU] Fix .Lfunc_end label placement (#191526)

2026-04-15 10:33:12 -07:00

AMDGPUAtomicOptimizer.cpp

…

AMDGPUAttributes.def

[AMDGPU] Change isSingleLaneExecution to account for WWM enabling lanes even if there's only one workitem (#188316)

2026-04-06 12:51:46 -04:00

AMDGPUAttributor.cpp

AMDGPU: Stop creating attributor attributes for declarations (#190800)

2026-04-07 15:51:45 +00:00

AMDGPUBarrierLatency.cpp

…

AMDGPUBarrierLatency.h

…

AMDGPUCallingConv.td

…

AMDGPUCallLowering.cpp

…

AMDGPUCallLowering.h

…

AMDGPUCodeGenPrepare.cpp

[IRBuilder][NFC] Add CreateFAbs helper (#193421)

2026-04-22 10:50:17 +01:00

AMDGPUCoExecSchedStrategy.cpp

[AMDGPU] Enable lane masks tracking in coexec scheduler. (#194578)

2026-04-28 17:50:29 +02:00

AMDGPUCoExecSchedStrategy.h

Reapply "[AMDGPU] Add HWUI pressure heuristics to coexec strategy (#184929)" (#189121)

2026-03-30 12:18:29 -07:00

AMDGPUCombine.td

…

AMDGPUCombinerHelper.cpp

Reland "[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) (#155107)" (#188502)

2026-04-04 05:57:13 -07:00

AMDGPUCombinerHelper.h

…

AMDGPUCtorDtorLowering.cpp

…

AMDGPUCtorDtorLowering.h

…

AMDGPUExportClustering.cpp

…

AMDGPUExportClustering.h

…

AMDGPUExportKernelRuntimeHandles.cpp

…

AMDGPUExportKernelRuntimeHandles.h

…

AMDGPUFeatures.td

…

AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUGenRegisterBankInfo.def

…

AMDGPUGISel.td

…

AMDGPUGlobalISelDivergenceLowering.cpp

[NFC][AMDGPU] Move PhiLoweringHelper and related types into AMDGPU namespace (#192586)

2026-04-20 14:06:42 +01:00

AMDGPUGlobalISelUtils.cpp

…

AMDGPUGlobalISelUtils.h

…

AMDGPUHazardLatency.cpp

…

AMDGPUHazardLatency.h

…

AMDGPUHSAMetadataStreamer.cpp

…

AMDGPUHSAMetadataStreamer.h

…

AMDGPUIGroupLP.cpp

[AMDGPU] Add a sched group mask for LDSDMA instructions (#190872)

2026-04-23 08:44:32 -04:00

AMDGPUIGroupLP.h

[NFC][AMDGPU]: expose IGLPStrategyID in AMDGPUIGroupLP.h (#191340)

2026-04-09 23:02:28 -07:00

AMDGPUImageIntrinsicOptimizer.cpp

…

AMDGPUInsertDelayAlu.cpp

…

AMDGPUInstCombineIntrinsic.cpp

ValueTracking: Use SimplifyQuery for computeConstantRange (#191726)

2026-04-20 11:49:30 +01:00

AMDGPUInstrInfo.cpp

…

AMDGPUInstrInfo.h

…

AMDGPUInstrInfo.td

…

AMDGPUInstructions.td

[AMDGPU] Prefer mul24 over mad24 on SDWA targets (#193033)

2026-04-21 11:29:14 +00:00

AMDGPUInstructionSelector.cpp

[AMDGPU] Emit s_barrier_signal for s.barrier.signal.var when able (#191028)

2026-04-08 16:22:30 -07:00

AMDGPUInstructionSelector.h

…

AMDGPUISelDAGToDAG.cpp

[AMDGPU] Prefer mul24 over mad24 on SDWA targets (#193033)

2026-04-21 11:29:14 +00:00

AMDGPUISelDAGToDAG.h

[AMDGPU] Prefer mul24 over mad24 on SDWA targets (#193033)

2026-04-21 11:29:14 +00:00

AMDGPUISelLowering.cpp

[AMDGPU] performSraCombine - SRA(X,BW-1) - don't freeze HI operand for single (repeated) shift (#193468)

2026-04-22 12:01:18 +00:00

AMDGPUISelLowering.h

[AtomicExpandPass] Preserve atomic and volatile nature of emulated operations (#188361)

2026-04-30 09:31:39 -07:00

AMDGPULaneMaskUtils.h

…

AMDGPULateCodeGenPrepare.cpp

…

AMDGPULegalizerInfo.cpp

AMDGPU: Skip last corrections in afn f64 reciprocal (#183696)

2026-04-22 21:59:45 +01:00

AMDGPULegalizerInfo.h

…

AMDGPULibCalls.cpp

[IRBuilder][NFC] Add CreateFAbs helper (#193421)

2026-04-22 10:50:17 +01:00

AMDGPULibFunc.cpp

…

AMDGPULibFunc.h

…

AMDGPULowerBufferFatPointers.cpp

…

AMDGPULowerExecSync.cpp

[AMDGPU] Add object linking support for LDS and named barrier lowering in the middle end (#191645)

2026-04-14 20:28:17 -04:00

AMDGPULowerIntrinsics.cpp

[AMDGPU] Preserve metadata in all barrier lowering paths (#191916)

2026-04-13 19:07:57 -07:00

AMDGPULowerKernelArguments.cpp

[AMDGPU] Add !noalias metadata to mem-accessing calls w/o pointer args (#188949)

2026-04-03 08:41:05 +02:00

AMDGPULowerKernelAttributes.cpp

…

AMDGPULowerModuleLDSPass.cpp

[NFC][AMDGPU] Remove amdgpu-link-time-lds module flag (#193806)

2026-04-23 14:31:21 -04:00

AMDGPULowerVGPREncoding.cpp

[AMDGPU] Preserve old MSBs when handling SETREG (#191352)

2026-04-30 03:09:33 -07:00

AMDGPULowerVGPREncoding.h

…

AMDGPUMachineFunctionInfo.cpp

…

AMDGPUMachineFunctionInfo.h

…

AMDGPUMachineModuleInfo.cpp

…

AMDGPUMachineModuleInfo.h

…

AMDGPUMacroFusion.cpp

…

AMDGPUMacroFusion.h

…

AMDGPUMarkLastScratchLoad.cpp

…

AMDGPUMCInstLower.cpp

Reapply "AMDGPU: Implement getInstSizeVerifyMode" (#194026) (#194362)

2026-04-27 15:15:40 +00:00

AMDGPUMCInstLower.h

…

AMDGPUMCResourceInfo.cpp

[MC] Make MCContext::getAsmInfo return a reference. NFC (#194523)

2026-04-28 03:57:47 +00:00

AMDGPUMCResourceInfo.h

[AMDGPU] Report only local per-function resource usage when object linking is enabled (#192594)

2026-04-20 16:49:59 +00:00

AMDGPUMemoryUtils.cpp

…

AMDGPUMemoryUtils.h

…

AMDGPUMIRFormatter.cpp

[AMDGPU][MIRFormatter] Printer & parser for S_WAITCNT human-readable mask (#193895)

2026-04-28 14:34:46 -07:00

AMDGPUMIRFormatter.h

[AMDGPU][MIRFormatter] Printer & parser for S_WAITCNT human-readable mask (#193895)

2026-04-28 14:34:46 -07:00

AMDGPUNextUseAnalysis.cpp

AMDGPU: Add NextUseAnalysis Pass (#178873)

2026-04-16 12:05:59 -05:00

AMDGPUNextUseAnalysis.h

AMDGPU: Add NextUseAnalysis Pass (#178873)

2026-04-16 12:05:59 -05:00

AMDGPUPassRegistry.def

AMDGPU: Add NextUseAnalysis Pass (#178873)

2026-04-16 12:05:59 -05:00

AMDGPUPerfHintAnalysis.cpp

…

AMDGPUPerfHintAnalysis.h

…

AMDGPUPostLegalizerCombiner.cpp

[NFC] Removes unused Combiner dependency on TargetPassConfig (#188365)

2026-03-30 08:58:22 -07:00

AMDGPUPredicateControl.td

…

AMDGPUPreLegalizerCombiner.cpp

[NFC] Removes unused Combiner dependency on TargetPassConfig (#188365)

2026-03-30 08:58:22 -07:00

AMDGPUPreloadKernArgProlog.cpp

…

AMDGPUPreloadKernArgProlog.h

…

AMDGPUPreloadKernelArguments.cpp

…

AMDGPUPrepareAGPRAlloc.cpp

…

AMDGPUPrepareAGPRAlloc.h

…

AMDGPUPrintfRuntimeBinding.cpp

…

AMDGPUPromoteAlloca.cpp

AMDGPU: Make VarIndex WeakTrackingVH in AMDGPUPromoteAlloca (#188921)

2026-03-28 09:50:25 +08:00

AMDGPUPromoteKernelArguments.cpp

…

AMDGPUPTNote.h

…

AMDGPURegBankCombiner.cpp

[GISel] Use GISelValueTracking in isKnownNeverNaN (#190542)

2026-04-13 13:42:12 +00:00

AMDGPURegBankLegalize.cpp

AMDGPU/GlobalISel: RegbankLegalize rules for merge-like opcodes (#193026)

2026-04-21 12:35:47 +02:00

AMDGPURegBankLegalizeHelper.cpp

[AMDGPU][NFC] Use LaneMaskConstants for waterfall loops in AMDGPURegBankLegalizeHelper (#190792)

2026-04-30 10:24:49 +00:00

AMDGPURegBankLegalizeHelper.h

AMDGPU/GlobalISel: RegBankLegalize AGPR support and gfx908 MFMA rules (#192603)

2026-04-22 23:01:03 -07:00

AMDGPURegBankLegalizeRules.cpp

[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_sqrt (#194231)

2026-04-30 13:24:55 +00:00

AMDGPURegBankLegalizeRules.h

AMDGPU/GlobalISel: RegBankLegalize AGPR support and gfx908 MFMA rules (#192603)

2026-04-22 23:01:03 -07:00

AMDGPURegBankSelect.cpp

…

AMDGPURegisterBankInfo.cpp

[AMDGPU] Fix async operations in GlobalISel on gfx12-plus (#190776)

2026-04-08 10:11:50 +00:00

AMDGPURegisterBankInfo.h

…

AMDGPURegisterBanks.td

…

AMDGPURemoveIncompatibleFunctions.cpp

…

AMDGPURemoveIncompatibleFunctions.h

…

AMDGPUReserveWWMRegs.cpp

…

AMDGPUReserveWWMRegs.h

…

AMDGPUResourceUsageAnalysis.cpp

[AMDGPU] Report only local per-function resource usage when object linking is enabled (#192594)

2026-04-20 16:49:59 +00:00

AMDGPUResourceUsageAnalysis.h

…

AMDGPURewriteAGPRCopyMFMA.cpp

[AMDGPU] Reland "Fixed verifier crash because of multiple live range components." (#190719) (#193286)

2026-04-21 12:33:24 -07:00

AMDGPURewriteOutArguments.cpp

…

AMDGPURewriteUndefForPHI.cpp

…

AMDGPUSearchableTables.td

AMDGPU: ds.atomic.barrier.arrive.rtn.b64 is a source of divergence (#192765)

2026-04-21 08:56:34 -07:00

AMDGPUSelectionDAGInfo.cpp

…

AMDGPUSelectionDAGInfo.h

[AMDGPU] Disable generic DAG combines at -O0 to preserve debuggability. (#176304)

2026-04-01 11:55:17 +02:00

AMDGPUSetWavePriority.cpp

…

AMDGPUSplitModule.cpp

[NFC] Move TimePasses globals from Pass.h to PassTimingInfo.h (#192352)

2026-04-15 22:58:20 +00:00

AMDGPUSplitModule.h

…

AMDGPUSubtarget.cpp

[AMDGPU] Use wavefront scope for single-wave workgroup synchronization (#187673)

2026-04-09 13:33:13 +02:00

AMDGPUSubtarget.h

[AMDGPU] Use wavefront scope for single-wave workgroup synchronization (#187673)

2026-04-09 13:33:13 +02:00

AMDGPUSwLowerLDS.cpp

[AMDGPU][ASAN] Move allocas to entry block in amdgpu-sw-lower-lds pass (#190772)

2026-04-17 11:14:49 +05:30

AMDGPUTargetMachine.cpp

[AMDGPU][NFC] Eliminates the redundant code in the AMDGPUTargetMachine.cpp (#193169)

2026-04-22 12:52:17 +05:30

AMDGPUTargetMachine.h

[AMDGPU] Add object linking support for LDS and named barrier lowering in the middle end (#191645)

2026-04-14 20:28:17 -04:00

AMDGPUTargetObjectFile.cpp

…

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

[LoopUnroll] Enable allowexpensivetripcounts when user provides pragma (#181267)

2026-04-09 09:35:52 -05:00

AMDGPUTargetTransformInfo.h

[CostModel] Move default expand cost for partial reductions to BasicTTIImpl (#189905)

2026-04-02 09:42:53 +01:00

AMDGPUUniformIntrinsicCombine.cpp

…

AMDGPUUnifyDivergentExitNodes.cpp

[NFC][AMDGPU] Rename AMDGPUUnifyDivergentExitNodes to AMDGPUUnifyDivergentExitNodesLegacy (#192399)

2026-04-16 16:54:54 +01:00

AMDGPUUnifyDivergentExitNodes.h

…

AMDGPUWaitcntUtils.cpp

[AMDGPU][NFC] Move InstCounterType and Waitcnt to AMDGPUWaitcntUtils.h (#187823)

2026-04-08 10:37:26 -07:00

AMDGPUWaitcntUtils.h

[AMDGPU][NFC] Move InstCounterType and Waitcnt to AMDGPUWaitcntUtils.h (#187823)

2026-04-08 10:37:26 -07:00

AMDGPUWaitSGPRHazards.cpp

…

AMDGPUWaitSGPRHazards.h

…

AMDKernelCodeT.h

…

BUFInstructions.td

…

CaymanInstructions.td

…

CMakeLists.txt

AMDGPU: Add NextUseAnalysis Pass (#178873)

2026-04-16 12:05:59 -05:00

DSDIRInstructions.td

…

DSInstructions.td

…

EvergreenInstructions.td

…

EXPInstructions.td

…

FLATInstructions.td

[AMDGPU] Fix i16/i8 flat store in true16 with sramecc (#190238)

2026-04-02 17:32:50 -07:00

GCNCreateVOPD.cpp

…

GCNDPPCombine.cpp

…

GCNDPPCombine.h

…

GCNHazardRecognizer.cpp

[AMDGPU][NFC] Move InstCounterType and Waitcnt to AMDGPUWaitcntUtils.h (#187823)

2026-04-08 10:37:26 -07:00

GCNHazardRecognizer.h

…

GCNILPSched.cpp

…

GCNIterativeScheduler.cpp

…

GCNIterativeScheduler.h

…

GCNMinRegStrategy.cpp

…

GCNNSAReassign.cpp

…

GCNNSAReassign.h

…

GCNPreRALongBranchReg.cpp

…

GCNPreRALongBranchReg.h

…

GCNPreRAOptimizations.cpp

…

GCNPreRAOptimizations.h

…

GCNProcessors.td

[AMDGPU] Define new targets gfx1171 and gfx1172 (#187735)

2026-04-01 18:16:11 +02:00

GCNRegPressure.cpp

[AMDGPU][Scheduler] Prepare remat stage for rematerializer integration (NFC) (#189489)

2026-04-11 15:38:44 +00:00

GCNRegPressure.h

[AMDGPU][Scheduler] Prepare remat stage for rematerializer integration (NFC) (#189489)

2026-04-11 15:38:44 +00:00

GCNRewritePartialRegUses.cpp

…

GCNRewritePartialRegUses.h

…

GCNSchedStrategy.cpp

Re-apply "[AMDGPU][Scheduler] Use MIR-level rematerializer in rematerialization stage (#189491)" (#192443)

2026-04-23 19:11:37 +02:00

GCNSchedStrategy.h

Re-apply "[AMDGPU][Scheduler] Use MIR-level rematerializer in rematerialization stage (#189491)" (#192443)

2026-04-23 19:11:37 +02:00

GCNSubtarget.cpp

[AMDGPU] misched: avoid subregister dependencies (#140255)

2026-04-23 14:32:43 +02:00

GCNSubtarget.h

[AMDGPU] misched: avoid subregister dependencies (#140255)

2026-04-23 14:32:43 +02:00

GCNVOPDUtils.cpp

AMDGPU: Use SmallSet for VOPD scalar reg tracking (#190650)

2026-04-07 12:57:45 +02:00

GCNVOPDUtils.h

…

MIMGInstructions.td

[LLVM][Intrinsics] Refactor IIT encoding generation (#189790)

2026-04-01 06:39:36 -07:00

R600.h

…

R600.td

…

R600AsmPrinter.cpp

…

R600AsmPrinter.h

…

R600ClauseMergePass.cpp

…

R600ControlFlowFinalizer.cpp

…

R600Defines.h

…

R600EmitClauseMarkers.cpp

…

R600ExpandSpecialInstrs.cpp

…

R600FrameLowering.cpp

…

R600FrameLowering.h

…

R600InstrFormats.td

…

R600InstrInfo.cpp

…

R600InstrInfo.h

…

R600InstrInfo.td

…

R600Instructions.td

…

R600ISelDAGToDAG.cpp

…

R600ISelLowering.cpp

…

R600ISelLowering.h

[CodeGen] Add additional params to TargetLoweringBase::getTruncStoreAction (#187422)

2026-03-30 16:52:45 -07:00

R600MachineCFGStructurizer.cpp

…

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

…

R600MachineScheduler.cpp

…

R600MachineScheduler.h

…

R600MCInstLower.cpp

…

R600OpenCLImageTypeLoweringPass.cpp

…

R600OptimizeVectorRegisters.cpp

…

R600Packetizer.cpp

…

R600Processors.td

…

R600RegisterInfo.cpp

…

R600RegisterInfo.h

…

R600RegisterInfo.td

…

R600Schedule.td

…

R600Subtarget.cpp

…

R600Subtarget.h

…

R600TargetMachine.cpp

[AsmPrinter] Use AsmPrinterAnalysis to hold AsmPrinter

2026-04-11 10:35:07 -07:00

R600TargetMachine.h

[AsmPrinter] Use AsmPrinterAnalysis to hold AsmPrinter

2026-04-11 10:35:07 -07:00

R600TargetTransformInfo.cpp

…

R600TargetTransformInfo.h

Fix buildbot failure by explicitly disabling partial reductions in TTI. (#190165)

2026-04-03 16:33:39 +01:00

R700Instructions.td

…

SIAnnotateControlFlow.cpp

…

SIDefines.h

[AMDGPU][MC] update USER_SGPR_COUNT bits for GFX1250 (#192579)

2026-04-28 21:25:29 -07:00

SIFixSGPRCopies.cpp

[AMDGPU] Generate waterfall for calls with SGPR(inreg) argument (#146997)

2026-04-20 08:43:22 +08:00

SIFixSGPRCopies.h

…

SIFixVGPRCopies.cpp

…

SIFixVGPRCopies.h

…

SIFoldOperands.cpp

[AMDGPU][SIFoldOperands] Fix OR -1 fold (#189655)

2026-04-01 13:37:37 +01:00

SIFoldOperands.h

…

SIFormMemoryClauses.cpp

…

SIFormMemoryClauses.h

…

SIFrameLowering.cpp

AMDGPU: Don't save FP/BP for noreturn functions (#187668)

2026-04-20 12:00:14 +02:00

SIFrameLowering.h

…

SIInsertHardClauses.cpp

…

SIInsertWaitcnts.cpp

[AMDGPU] Mark ASYNCMARK as meta instruction to fix hazard cycle miscounting (#189981)

2026-04-17 17:58:23 +00:00

SIInstrFormats.td

…

SIInstrInfo.cpp

Reapply "AMDGPU: Implement getInstSizeVerifyMode" (#194026) (#194362)

2026-04-27 15:15:40 +00:00

SIInstrInfo.h

Reapply "AMDGPU: Implement getInstSizeVerifyMode" (#194026) (#194362)

2026-04-27 15:15:40 +00:00

SIInstrInfo.td

[AMDGPU][MC] Allow the nolds modifier (#185129)

2026-04-24 14:08:10 -07:00

SIInstructions.td

[AMDGPU] Add true16 patterns for build_vector (vgpr, 0) (#192147)

2026-04-15 15:03:24 -07:00

SIISelLowering.cpp

[AMDGPU] Add readfirstlane for inline asm SGPR with VGPR input (#176330)

2026-04-30 12:45:20 -05:00

SIISelLowering.h

[AMDGPU] Add readfirstlane for inline asm SGPR with VGPR input (#176330)

2026-04-30 12:45:20 -05:00

SILateBranchLowering.cpp

…

SILoadStoreOptimizer.cpp

…

SILoadStoreOptimizer.h

…

SILowerControlFlow.cpp

…

SILowerControlFlow.h

…

SILowerI1Copies.cpp

[MachineSSAUpdater][AMDGPU] Add faster version of MachineSSAUpdater class. (#145722)

2026-04-24 13:25:51 +02:00

SILowerI1Copies.h

[NFC][AMDGPU] Move PhiLoweringHelper and related types into AMDGPU namespace (#192586)

2026-04-20 14:06:42 +01:00

SILowerSGPRSpills.cpp

[AMDGPU][SILowerSGPRSpills] Correct insertion of IMPLICIT_DEF in cycles (#186348)

2026-04-07 07:14:38 +01:00

SILowerSGPRSpills.h

…

SILowerWWMCopies.cpp

…

SILowerWWMCopies.h

…

SIMachineFunctionInfo.cpp

[NFC][AMDGPU] Fix a compiler warning caused by a small typo (#191107)

2026-04-09 08:54:16 -04:00

SIMachineFunctionInfo.h

…

SIMachineScheduler.cpp

…

SIMachineScheduler.h

…

SIMemoryLegalizer.cpp

[AMDGPU] Use wavefront scope for single-wave workgroup synchronization (#187673)

2026-04-09 13:33:13 +02:00

SIModeRegister.cpp

…

SIModeRegisterDefaults.cpp

…

SIModeRegisterDefaults.h

…

SIOptimizeExecMasking.cpp

…

SIOptimizeExecMasking.h

…

SIOptimizeExecMaskingPreRA.cpp

…

SIOptimizeExecMaskingPreRA.h

…

SIOptimizeVGPRLiveRange.cpp

…

SIOptimizeVGPRLiveRange.h

…

SIPeepholeSDWA.cpp

…

SIPeepholeSDWA.h

…

SIPostRABundler.cpp

…

SIPostRABundler.h

…

SIPreAllocateWWMRegs.cpp

…

SIPreAllocateWWMRegs.h

…

SIPreEmitPeephole.cpp

…

SIProgramInfo.cpp

[NFC] typo fixes (#194908)

2026-04-29 12:52:59 -04:00

SIProgramInfo.h

[AMDGPU][MC] update USER_SGPR_COUNT bits for GFX1250 (#192579)

2026-04-28 21:25:29 -07:00

SIRegisterInfo.cpp

[AMDGPU] Fix s_cselect scc clobber issue (#193498)

2026-04-23 08:45:37 -05:00

SIRegisterInfo.h

…

SIRegisterInfo.td

…

SISchedule.td

[AMDGPU] Update gfx12 sched model (#192448)

2026-04-16 16:22:30 +02:00

SIShrinkInstructions.cpp

Reland "[AMDGPU] Generate more swaps" #184164 (#192452)

2026-04-17 08:42:35 -05:00

SIShrinkInstructions.h

…

SISpillUtils.cpp

[AMDGPU] Fix crash with dead frame indices in debug values (#183297)

2026-04-01 13:41:53 +01:00

SISpillUtils.h

[AMDGPU] Fix crash with dead frame indices in debug values (#183297)

2026-04-01 13:41:53 +01:00

SIWholeQuadMode.cpp

AMDGPU: Back-propagate wqm for sources of side-effect instruction (#193395)

2026-04-27 12:42:41 +08:00

SIWholeQuadMode.h

…

SMInstructions.td

…

SOPInstructions.td

[AMDGPU] Mark WAIT_ASYNCMARK as zero-size instruction (#195107)

2026-04-30 17:42:21 +01:00

VIInstrFormats.td

…

VINTERPInstructions.td

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VOP1Instructions.td

Revert "[AMDGPU][True16] add true16 pattern for cvt_pk_fp32_f8 (#1800… (#191835)

2026-04-13 14:27:37 -04:00

VOP2Instructions.td

AMDGPU/GlobalISel: Fix G_STRICT_FMUL f64 selection on GFX12 (#195050)

2026-04-30 12:59:52 +02:00

VOP3Instructions.td

[AMDGPU] Use WriteSALUDummy for v_div_scale* (#191670)

2026-04-13 09:42:16 -07:00

VOP3PInstructions.td

[AMDGPU] misched: avoid subregister dependencies (#140255)

2026-04-23 14:32:43 +02:00

VOPCInstructions.td

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VOPDInstructions.td

[AMDGPU][MC] Permit unneeded VOPD mov operands to be non-zero (#194060)

2026-04-27 09:46:18 -04:00

VOPInstructions.td

Revert "AMDGPU: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3" (#190159)

2026-04-02 14:05:08 +00:00