d8ef5bcc87
Add `getCPUAndFeaturesAttributes` to `CIRGenModule`, mirroring OGCG's `GetCPUAndFeaturesAttributes`. This sets `cir.target-cpu`, `cir.target-features` and `cir.tune-cpu` string attributes on `cir.func`. For AMDGPU, only features that differ from the target CPU's defaults are emitted matching OGCG.
90 lines
3.9 KiB
C++
90 lines
3.9 KiB
C++
#include "../CodeGenCUDA/Inputs/cuda.h"
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir \
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// RUN: -x hip -fhip-new-launch-api \
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// RUN: -I%S/../CodeGenCUDA/Inputs/ -emit-cir %s -o %t.cir
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// RUN: FileCheck --check-prefix=CIR-HOST --input-file=%t.cir %s
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// RUN: %clang_cc1 -triple=amdgcn-amd-amdhsa -x hip -fclangir \
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// RUN: -fcuda-is-device -fhip-new-launch-api \
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// RUN: -I%S/../CodeGenCUDA/Inputs/ -emit-cir %s -o %t.cir
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// RUN: FileCheck --check-prefix=CIR-DEVICE --input-file=%t.cir %s
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu \
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// RUN: -x hip -emit-llvm -fhip-new-launch-api \
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// RUN: -I%S/../CodeGenCUDA/Inputs/ %s -o %t.ll
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// RUN: FileCheck --check-prefix=OGCG-HOST --input-file=%t.ll %s
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// RUN: %clang_cc1 -triple=amdgcn-amd-amdhsa -x hip \
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// RUN: -fcuda-is-device -fhip-new-launch-api \
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// RUN: -fvisibility=hidden \
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// RUN: -I%S/../CodeGenCUDA/Inputs/ -emit-llvm %s -o %t.ll
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// RUN: FileCheck --check-prefix=OGCG-DEVICE --input-file=%t.ll %s
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// Per Thread Stream test cases:
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu \
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// RUN: -fgpu-default-stream=per-thread -DHIP_API_PER_THREAD_DEFAULT_STREAM \
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// RUN: -x hip -emit-llvm -fhip-new-launch-api \
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// RUN: -I%S/../CodeGenCUDA/Inputs/ %s -o %t.ll
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// RUN: FileCheck --check-prefix=OGCG-HOST-PTH --input-file=%t.ll %s
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__host__ void host_fn(int *a, int *b, int *c) {}
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// CIR-HOST: cir.func {{.*}}{{.*}} @_Z7host_fnPiS_S_
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// CIR-DEVICE-NOT: cir.func {{.*}}{{.*}} @_Z7host_fnPiS_S_
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__device__ void device_fn(int* a, double b, float c) {}
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// CIR-HOST-NOT: cir.func {{.*}}{{.*}} @_Z9device_fnPidf
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// CIR-DEVICE: cir.func {{.*}}{{.*}} @_Z9device_fnPidf
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__global__ void global_fn(int a) {}
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// CIR-DEVICE: cir.func {{.*}}{{.*}} @_Z9global_fni
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// OGCG-DEVICE: define protected amdgpu_kernel void @_Z9global_fni
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// CIR-HOST: @_Z24__device_stub__global_fni{{.*}}attributes {{{.*}}cu.kernel_name = #cir.cu.kernel_name<"_Z9global_fni">{{.*}}}
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// CIR-HOST: %[[#CIRKernelArgs:]] = cir.alloca {{.*}}"kernel_args"
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// CIR-HOST: %[[#Decayed:]] = cir.cast array_to_ptrdecay %[[#CIRKernelArgs]]
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// CIR-HOST: cir.call @__hipPopCallConfiguration
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// CIR-HOST: cir.get_global @_Z9global_fni : !cir.ptr<!cir.func<(!s32i)>>
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// CIR-HOST: cir.call @hipLaunchKernel
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// OGCG-HOST: define dso_local void @_Z24__device_stub__global_fni
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// OGCG-HOST: %kernel_args = alloca ptr, i64 1, align 16
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// OGCG-HOST: getelementptr ptr, ptr %kernel_args, i32 0
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// OGCG-HOST: call i32 @__hipPopCallConfiguration
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// OGCG-HOST: %call = call noundef i32 @hipLaunchKernel(ptr noundef @_Z9global_fni
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// OGCG-HOST-PTH: %call = call noundef i32 @hipLaunchKernel_spt(ptr noundef @_Z9global_fni
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int main() {
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global_fn<<<1, 1>>>(1);
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}
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// CIR-DEVICE-NOT: cir.func {{.*}}{{.*}} @main()
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// CIR-HOST: cir.func {{.*}}{{.*}} @main()
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// CIR-HOST: cir.call @_ZN4dim3C1Ejjj
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// CIR-HOST: cir.call @_ZN4dim3C1Ejjj
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// CIR-HOST: [[Push:%[0-9]+]] = cir.call @__hipPushCallConfiguration
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// CIR-HOST: [[ConfigOK:%[0-9]+]] = cir.cast int_to_bool [[Push]]
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// CIR-HOST: cir.if [[ConfigOK]] {
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// CIR-HOST: } else {
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// CIR-HOST: [[Arg:%[0-9]+]] = cir.const #cir.int<1>
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// CIR-HOST: cir.call @_Z24__device_stub__global_fni([[Arg]])
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// CIR-HOST: }
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// OGCG-HOST: define dso_local noundef i32 @main
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// OGCG-HOST: %agg.tmp = alloca %struct.dim3, align 4
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// OGCG-HOST: %agg.tmp1 = alloca %struct.dim3, align 4
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// OGCG-HOST: call void @_ZN4dim3C1Ejjj
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// OGCG-HOST: call void @_ZN4dim3C1Ejjj
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// OGCG-HOST: %call = call i32 @__hipPushCallConfiguration
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// OGCG-HOST: %tobool = icmp ne i32 %call, 0
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// OGCG-HOST: br i1 %tobool, label %kcall.end, label %kcall.configok
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// OGCG-HOST: kcall.configok:
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// OGCG-HOST: call void @_Z24__device_stub__global_fni(i32 noundef 1)
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// OGCG-HOST: br label %kcall.end
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// OGCG-HOST: kcall.end:
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// OGCG-HOST: %{{[0-9]+}} = load i32, ptr %retval, align 4
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// OGCG-HOST: ret i32 %8
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