6654737d9a
This patch optimizes the creation of constant 64-bit vectors (e.g., v2i32, v4i16) by avoiding expensive loads from the constant pool. The optimization works by packing the constant vector elements into a single i64 immediate and bitcasting the result to the target vector type. This replaces a memory access with more efficient immediate materialization. To ensure this transformation is efficient, a check is performed to verify that the immediate can be generated in two or fewer mov instructions. If it requires more, the compiler falls back to using the constant pool. The optimization is disabled for bigendian targets for now.
178 lines
4.6 KiB
LLVM
178 lines
4.6 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=CHECK
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; LEGAL INTEGER TYPES
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define <2 x i64> @stepvector_v2i64() {
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; CHECK-LABEL: .LCPI0_0:
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; CHECK-NEXT: .xword 0
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; CHECK-NEXT: .xword 1
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; CHECK-LABEL: stepvector_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: ret
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entry:
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%0 = call <2 x i64> @llvm.stepvector.v2i64()
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ret <2 x i64> %0
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}
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define <4 x i32> @stepvector_v4i32() {
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; CHECK-LABEL: .LCPI1_0:
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; CHECK-NEXT: .word 0
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; CHECK-NEXT: .word 1
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; CHECK-NEXT: .word 2
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; CHECK-NEXT: .word 3
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; CHECK-LABEL: stepvector_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: ret
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entry:
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%0 = call <4 x i32> @llvm.stepvector.v4i32()
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ret <4 x i32> %0
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}
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define <8 x i16> @stepvector_v8i16() {
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; CHECK-LABEL: .LCPI2_0:
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; CHECK-NEXT: .hword 0
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; CHECK-NEXT: .hword 1
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; CHECK-NEXT: .hword 2
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; CHECK-NEXT: .hword 3
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; CHECK-NEXT: .hword 4
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; CHECK-NEXT: .hword 5
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; CHECK-NEXT: .hword 6
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; CHECK-NEXT: .hword 7
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; CHECK-LABEL: stepvector_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI2_0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI2_0]
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; CHECK-NEXT: ret
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entry:
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%0 = call <8 x i16> @llvm.stepvector.v8i16()
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ret <8 x i16> %0
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}
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define <16 x i8> @stepvector_v16i8() {
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; CHECK-LABEL: .LCPI3_0:
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 6
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; CHECK-NEXT: .byte 7
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .byte 9
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; CHECK-NEXT: .byte 10
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; CHECK-NEXT: .byte 11
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; CHECK-NEXT: .byte 12
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; CHECK-NEXT: .byte 13
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; CHECK-NEXT: .byte 14
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; CHECK-NEXT: .byte 15
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; CHECK-LABEL: stepvector_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: ret
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entry:
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%0 = call <16 x i8> @llvm.stepvector.v16i8()
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ret <16 x i8> %0
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}
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; ILLEGAL INTEGER TYPES
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define <4 x i64> @stepvector_v4i64() {
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; CHECK-LABEL: .LCPI4_0:
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; CHECK-NEXT: .xword 0
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; CHECK-NEXT: .xword 1
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; CHECK-LABEL: .LCPI4_1:
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; CHECK-NEXT: .xword 2
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; CHECK-NEXT: .xword 3
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; CHECK-LABEL: stepvector_v4i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: adrp x9, .LCPI4_1
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI4_1]
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; CHECK-NEXT: ret
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entry:
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%0 = call <4 x i64> @llvm.stepvector.v4i64()
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ret <4 x i64> %0
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}
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define <16 x i32> @stepvector_v16i32() {
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; CHECK-LABEL: .LCPI5_0:
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; CHECK-NEXT: .word 0
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; CHECK-NEXT: .word 1
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; CHECK-NEXT: .word 2
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; CHECK-NEXT: .word 3
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; CHECK-LABEL: .LCPI5_1:
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; CHECK-NEXT: .word 4
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; CHECK-NEXT: .word 5
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; CHECK-NEXT: .word 6
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; CHECK-NEXT: .word 7
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; CHECK-LABEL: .LCPI5_2:
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; CHECK-NEXT: .word 8
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; CHECK-NEXT: .word 9
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; CHECK-NEXT: .word 10
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; CHECK-NEXT: .word 11
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; CHECK-LABEL: .LCPI5_3:
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; CHECK-NEXT: .word 12
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; CHECK-NEXT: .word 13
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; CHECK-NEXT: .word 14
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; CHECK-NEXT: .word 15
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; CHECK-LABEL: stepvector_v16i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI5_0
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; CHECK-NEXT: adrp x9, .LCPI5_1
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; CHECK-NEXT: adrp x10, .LCPI5_2
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; CHECK-NEXT: adrp x11, .LCPI5_3
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI5_0]
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; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI5_1]
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; CHECK-NEXT: ldr q2, [x10, :lo12:.LCPI5_2]
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; CHECK-NEXT: ldr q3, [x11, :lo12:.LCPI5_3]
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; CHECK-NEXT: ret
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entry:
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%0 = call <16 x i32> @llvm.stepvector.v16i32()
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ret <16 x i32> %0
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}
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define <2 x i32> @stepvector_v2i32() {
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; CHECK-LABEL: stepvector_v2i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x8, #4294967296 // =0x100000000
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: ret
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entry:
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%0 = call <2 x i32> @llvm.stepvector.v2i32()
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ret <2 x i32> %0
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}
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define <4 x i16> @stepvector_v4i16() {
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; CHECK-LABEL: .LCPI7_0:
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; CHECK-NEXT: .hword 0
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; CHECK-NEXT: .hword 1
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; CHECK-NEXT: .hword 2
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; CHECK-NEXT: .hword 3
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; CHECK-LABEL: stepvector_v4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI7_0
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; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI7_0]
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; CHECK-NEXT: ret
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entry:
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%0 = call <4 x i16> @llvm.stepvector.v4i16()
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ret <4 x i16> %0
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}
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declare <2 x i64> @llvm.stepvector.v2i64()
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declare <4 x i32> @llvm.stepvector.v4i32()
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declare <8 x i16> @llvm.stepvector.v8i16()
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declare <16 x i8> @llvm.stepvector.v16i8()
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declare <4 x i64> @llvm.stepvector.v4i64()
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declare <16 x i32> @llvm.stepvector.v16i32()
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declare <2 x i32> @llvm.stepvector.v2i32()
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declare <4 x i16> @llvm.stepvector.v4i16()
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