71de1e47c0
This reverts commit b7ce37c670.
The
[issue](https://github.com/llvm/llvm-project/pull/172837#issuecomment-3961532435)
this patch revealed was fixed by [this
patch](https://github.com/llvm/llvm-project/pull/183549).
262 lines
7.1 KiB
LLVM
262 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s --check-prefix=NEON
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; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+sve | FileCheck %s --check-prefix=SVE
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; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+cssc | FileCheck %s --check-prefix=CSSC
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; i256 popcount (register args, result truncated to i64)
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define i64 @ctpop_i256(i256 %a) nounwind {
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;
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;
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; NEON-LABEL: ctpop_i256:
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; NEON: // %bb.0:
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; NEON-NEXT: fmov d0, x2
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; NEON-NEXT: fmov d1, x0
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; NEON-NEXT: mov v0.d[1], x3
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; NEON-NEXT: mov v1.d[1], x1
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; NEON-NEXT: cnt v0.16b, v0.16b
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; NEON-NEXT: cnt v1.16b, v1.16b
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; NEON-NEXT: addv b0, v0.16b
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; NEON-NEXT: addv b1, v1.16b
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; NEON-NEXT: fmov x8, d0
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; NEON-NEXT: fmov x9, d1
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; NEON-NEXT: add x0, x9, x8
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; NEON-NEXT: ret
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;
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; SVE-LABEL: ctpop_i256:
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; SVE: // %bb.0:
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; SVE-NEXT: fmov d0, x2
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; SVE-NEXT: fmov d1, x0
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; SVE-NEXT: ptrue p0.d
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; SVE-NEXT: mov v0.d[1], x3
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; SVE-NEXT: mov v1.d[1], x1
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; SVE-NEXT: cnt z0.d, p0/m, z0.d
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; SVE-NEXT: cnt z1.d, p0/m, z1.d
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; SVE-NEXT: add v0.2d, v1.2d, v0.2d
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; SVE-NEXT: addp d0, v0.2d
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; SVE-NEXT: fmov x0, d0
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; SVE-NEXT: ret
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;
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; CSSC-LABEL: ctpop_i256:
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; CSSC: // %bb.0:
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; CSSC-NEXT: cnt x8, x3
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; CSSC-NEXT: cnt x9, x2
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; CSSC-NEXT: cnt x10, x1
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; CSSC-NEXT: cnt x11, x0
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; CSSC-NEXT: add x8, x9, x8
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; CSSC-NEXT: add x9, x11, x10
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; CSSC-NEXT: add x0, x9, x8
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; CSSC-NEXT: ret
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%pop = call i256 @llvm.ctpop.i256(i256 %a)
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%r = trunc i256 %pop to i64
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ret i64 %r
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}
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; i256 Hamming distance: popcount(x ^ y)
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define i64 @hamming_i256(i256 %a, i256 %b) nounwind {
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;
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;
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; NEON-LABEL: hamming_i256:
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; NEON: // %bb.0:
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; NEON-NEXT: eor x8, x0, x4
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; NEON-NEXT: eor x10, x2, x6
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; NEON-NEXT: eor x9, x1, x5
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; NEON-NEXT: fmov d0, x8
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; NEON-NEXT: fmov d1, x10
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; NEON-NEXT: eor x8, x3, x7
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; NEON-NEXT: mov v1.d[1], x8
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; NEON-NEXT: mov v0.d[1], x9
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; NEON-NEXT: cnt v1.16b, v1.16b
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; NEON-NEXT: cnt v0.16b, v0.16b
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; NEON-NEXT: addv b1, v1.16b
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; NEON-NEXT: addv b0, v0.16b
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; NEON-NEXT: fmov x8, d1
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; NEON-NEXT: fmov x9, d0
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; NEON-NEXT: add x0, x9, x8
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; NEON-NEXT: ret
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;
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; SVE-LABEL: hamming_i256:
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; SVE: // %bb.0:
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; SVE-NEXT: eor x8, x0, x4
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; SVE-NEXT: eor x10, x2, x6
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; SVE-NEXT: eor x9, x1, x5
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; SVE-NEXT: fmov d0, x8
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; SVE-NEXT: fmov d1, x10
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; SVE-NEXT: eor x8, x3, x7
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; SVE-NEXT: ptrue p0.d
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; SVE-NEXT: mov v1.d[1], x8
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; SVE-NEXT: mov v0.d[1], x9
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; SVE-NEXT: cnt z1.d, p0/m, z1.d
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; SVE-NEXT: cnt z0.d, p0/m, z0.d
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; SVE-NEXT: add v0.2d, v0.2d, v1.2d
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; SVE-NEXT: addp d0, v0.2d
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; SVE-NEXT: fmov x0, d0
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; SVE-NEXT: ret
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;
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; CSSC-LABEL: hamming_i256:
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; CSSC: // %bb.0:
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; CSSC-NEXT: eor x8, x3, x7
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; CSSC-NEXT: eor x9, x0, x4
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; CSSC-NEXT: eor x10, x1, x5
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; CSSC-NEXT: eor x11, x2, x6
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; CSSC-NEXT: cnt x8, x8
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; CSSC-NEXT: cnt x10, x10
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; CSSC-NEXT: cnt x11, x11
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; CSSC-NEXT: cnt x9, x9
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; CSSC-NEXT: add x8, x11, x8
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; CSSC-NEXT: add x9, x9, x10
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; CSSC-NEXT: add x0, x9, x8
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; CSSC-NEXT: ret
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%xor = xor i256 %a, %b
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%pop = call i256 @llvm.ctpop.i256(i256 %xor)
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%r = trunc i256 %pop to i64
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ret i64 %r
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}
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; i256 count leading zeros
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define i256 @ctlz_i256(i256 %a) nounwind {
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;
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;
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; NEON-LABEL: ctlz_i256:
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; NEON: // %bb.0:
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; NEON-NEXT: clz x8, x2
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; NEON-NEXT: clz x9, x3
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; NEON-NEXT: cmp x3, #0
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; NEON-NEXT: add x8, x8, #64
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; NEON-NEXT: clz x10, x0
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; NEON-NEXT: orr x11, x2, x3
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; NEON-NEXT: csel x8, x9, x8, ne
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; NEON-NEXT: clz x9, x1
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; NEON-NEXT: add x10, x10, #64
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; NEON-NEXT: cmp x1, #0
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; NEON-NEXT: mov x1, xzr
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; NEON-NEXT: mov x2, xzr
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; NEON-NEXT: csel x9, x9, x10, ne
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; NEON-NEXT: cmp x11, #0
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; NEON-NEXT: mov x3, xzr
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; NEON-NEXT: add x9, x9, #128
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; NEON-NEXT: csel x0, x8, x9, ne
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; NEON-NEXT: ret
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;
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; SVE-LABEL: ctlz_i256:
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; SVE: // %bb.0:
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; SVE-NEXT: clz x8, x2
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; SVE-NEXT: clz x9, x3
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; SVE-NEXT: cmp x3, #0
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; SVE-NEXT: add x8, x8, #64
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; SVE-NEXT: clz x10, x0
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; SVE-NEXT: orr x11, x2, x3
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; SVE-NEXT: csel x8, x9, x8, ne
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; SVE-NEXT: clz x9, x1
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; SVE-NEXT: add x10, x10, #64
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; SVE-NEXT: cmp x1, #0
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; SVE-NEXT: mov x1, xzr
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; SVE-NEXT: mov x2, xzr
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; SVE-NEXT: csel x9, x9, x10, ne
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; SVE-NEXT: cmp x11, #0
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; SVE-NEXT: mov x3, xzr
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; SVE-NEXT: add x9, x9, #128
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; SVE-NEXT: csel x0, x8, x9, ne
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; SVE-NEXT: ret
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;
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; CSSC-LABEL: ctlz_i256:
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; CSSC: // %bb.0:
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; CSSC-NEXT: clz x8, x2
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; CSSC-NEXT: clz x9, x3
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; CSSC-NEXT: cmp x3, #0
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; CSSC-NEXT: add x8, x8, #64
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; CSSC-NEXT: clz x10, x0
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; CSSC-NEXT: orr x11, x2, x3
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; CSSC-NEXT: csel x8, x9, x8, ne
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; CSSC-NEXT: clz x9, x1
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; CSSC-NEXT: add x10, x10, #64
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; CSSC-NEXT: cmp x1, #0
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; CSSC-NEXT: mov x1, xzr
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; CSSC-NEXT: mov x2, xzr
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; CSSC-NEXT: csel x9, x9, x10, ne
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; CSSC-NEXT: cmp x11, #0
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; CSSC-NEXT: mov x3, xzr
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; CSSC-NEXT: add x9, x9, #128
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; CSSC-NEXT: csel x0, x8, x9, ne
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; CSSC-NEXT: ret
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%r = call i256 @llvm.ctlz.i256(i256 %a, i1 false)
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ret i256 %r
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}
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; i256 count trailing zeros
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define i256 @cttz_i256(i256 %a) nounwind {
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;
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;
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; NEON-LABEL: cttz_i256:
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; NEON: // %bb.0:
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; NEON-NEXT: rbit x8, x1
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; NEON-NEXT: rbit x9, x0
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; NEON-NEXT: rbit x10, x3
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; NEON-NEXT: cmp x0, #0
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; NEON-NEXT: rbit x11, x2
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; NEON-NEXT: mov x3, xzr
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; NEON-NEXT: clz x8, x8
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; NEON-NEXT: clz x9, x9
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; NEON-NEXT: add x8, x8, #64
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; NEON-NEXT: csel x8, x9, x8, ne
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; NEON-NEXT: clz x9, x10
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; NEON-NEXT: clz x10, x11
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; NEON-NEXT: add x9, x9, #64
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; NEON-NEXT: cmp x2, #0
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; NEON-NEXT: orr x11, x0, x1
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; NEON-NEXT: csel x9, x10, x9, ne
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; NEON-NEXT: cmp x11, #0
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; NEON-NEXT: mov x1, xzr
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; NEON-NEXT: add x9, x9, #128
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; NEON-NEXT: mov x2, xzr
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; NEON-NEXT: csel x0, x8, x9, ne
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; NEON-NEXT: ret
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;
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; SVE-LABEL: cttz_i256:
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; SVE: // %bb.0:
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; SVE-NEXT: rbit x8, x1
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; SVE-NEXT: rbit x9, x0
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; SVE-NEXT: rbit x10, x3
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; SVE-NEXT: cmp x0, #0
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; SVE-NEXT: rbit x11, x2
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; SVE-NEXT: mov x3, xzr
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; SVE-NEXT: clz x8, x8
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; SVE-NEXT: clz x9, x9
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; SVE-NEXT: add x8, x8, #64
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; SVE-NEXT: csel x8, x9, x8, ne
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; SVE-NEXT: clz x9, x10
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; SVE-NEXT: clz x10, x11
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; SVE-NEXT: add x9, x9, #64
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; SVE-NEXT: cmp x2, #0
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; SVE-NEXT: orr x11, x0, x1
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; SVE-NEXT: csel x9, x10, x9, ne
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; SVE-NEXT: cmp x11, #0
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; SVE-NEXT: mov x1, xzr
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; SVE-NEXT: add x9, x9, #128
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; SVE-NEXT: mov x2, xzr
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; SVE-NEXT: csel x0, x8, x9, ne
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; SVE-NEXT: ret
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;
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; CSSC-LABEL: cttz_i256:
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; CSSC: // %bb.0:
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; CSSC-NEXT: ctz x8, x1
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; CSSC-NEXT: ctz x9, x0
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; CSSC-NEXT: cmp x0, #0
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; CSSC-NEXT: add x8, x8, #64
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; CSSC-NEXT: ctz x10, x3
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; CSSC-NEXT: orr x11, x0, x1
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; CSSC-NEXT: csel x8, x9, x8, ne
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; CSSC-NEXT: ctz x9, x2
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; CSSC-NEXT: add x10, x10, #64
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; CSSC-NEXT: cmp x2, #0
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; CSSC-NEXT: mov x1, xzr
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; CSSC-NEXT: mov x2, xzr
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; CSSC-NEXT: csel x9, x9, x10, ne
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; CSSC-NEXT: cmp x11, #0
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; CSSC-NEXT: mov x3, xzr
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; CSSC-NEXT: add x9, x9, #128
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; CSSC-NEXT: csel x0, x8, x9, ne
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; CSSC-NEXT: ret
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%r = call i256 @llvm.cttz.i256(i256 %a, i1 false)
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ret i256 %r
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}
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