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llvm-project/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi-strictfp.ll
Lukacma 817b7f3333 [NFC][AArch64] Split fptoi tests and add scal_to_vec convert tests (#179315) 
This patch splits simd-fptoi tests into strictfp and nonstrictfp files
for simplicity and adds tests which will test correct insertion of
bitcasts to certain scalar_to_vector variant which will be introduced in
#172837.
2026-02-23 14:23:58 +00:00

336 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK-SME
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK-SVE
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for fptosi_i32_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f32_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f32_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f32_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f32_simd
;
; FPTOI strictfp
;
define float @fptosi_i32_f16_simd(half %x) {
; CHECK-NOFPRCVT-LABEL: fptosi_i32_f16_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i32_f16_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, h0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptosi_i32_f16_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzs s0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptosi_i32_f16_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzs s0, h0
; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i32 %val to float
ret float %sum
}
define double @fptosi_i64_f16_simd(half %x) {
; CHECK-NOFPRCVT-LABEL: fptosi_i64_f16_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i64_f16_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, h0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptosi_i64_f16_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzs d0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptosi_i64_f16_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzs d0, h0
; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i64 %val to double
ret double %sum
}
define double @fptosi_i64_f32_simd(float %x) {
; CHECK-NOFPRCVT-LABEL: fptosi_i64_f32_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i64_f32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, s0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptosi_i64_f32_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzs d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptosi_i64_f32_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzs d0, s0
; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
}
define float @fptosi_i32_f64_simd(double %x) {
; CHECK-NOFPRCVT-LABEL: fptosi_i32_f64_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i32_f64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, d0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptosi_i32_f64_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzs s0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptosi_i32_f64_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzs s0, d0
; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
}
define double @fptosi_i64_f64_simd(double %x) {
; CHECK-NOFPRCVT-LABEL: fptosi_i64_f64_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i64_f64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptosi_i64_f64_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzs d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptosi_i64_f64_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzs d0, d0
; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
}
define float @fptosi_i32_f32_simd(float %x) {
; CHECK-NOFPRCVT-LABEL: fptosi_i32_f32_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i32_f32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptosi_i32_f32_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzs s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptosi_i32_f32_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzs s0, s0
; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
}
define float @fptoui_i32_f16_simd(half %x) {
; CHECK-NOFPRCVT-LABEL: fptoui_i32_f16_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h0
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i32_f16_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, h0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptoui_i32_f16_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzu s0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptoui_i32_f16_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzu s0, h0
; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i32 %val to float
ret float %sum
}
define double @fptoui_i64_f16_simd(half %x) {
; CHECK-NOFPRCVT-LABEL: fptoui_i64_f16_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i64_f16_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, h0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptoui_i64_f16_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzu d0, h0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptoui_i64_f16_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzu d0, h0
; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i64 %val to double
ret double %sum
}
define double @fptoui_i64_f32_simd(float %x) {
; CHECK-NOFPRCVT-LABEL: fptoui_i64_f32_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i64_f32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, s0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptoui_i64_f32_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzu d0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptoui_i64_f32_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzu d0, s0
; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
}
define float @fptoui_i32_f64_simd(double %x) {
; CHECK-NOFPRCVT-LABEL: fptoui_i32_f64_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i32_f64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, d0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptoui_i32_f64_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzu s0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptoui_i32_f64_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzu s0, d0
; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
}
define double @fptoui_i64_f64_simd(double %x) {
; CHECK-NOFPRCVT-LABEL: fptoui_i64_f64_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i64_f64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptoui_i64_f64_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzu d0, d0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptoui_i64_f64_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzu d0, d0
; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
}
define float @fptoui_i32_f32_simd(float %x) {
; CHECK-NOFPRCVT-LABEL: fptoui_i32_f32_simd:
; CHECK-NOFPRCVT: // %bb.0:
; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i32_f32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
;
; CHECK-SME-LABEL: fptoui_i32_f32_simd:
; CHECK-SME: // %bb.0:
; CHECK-SME-NEXT: fcvtzu s0, s0
; CHECK-SME-NEXT: ret
;
; CHECK-SVE-LABEL: fptoui_i32_f32_simd:
; CHECK-SVE: // %bb.0:
; CHECK-SVE-NEXT: fcvtzu s0, s0
; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
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