458e9c452c
Under certain conditions the LLVM `MipsDelaySlotFiller` fills a branch delay slot with an instruction requiring a load delay slot. However the `MipsDelaySlotFiller` does not check the filled instruction for hazard which leads to code like this: ```asm beqz $1, $BB0_5 lbu $2, %lo(_RNvCs5jWYnRsDZoD_3app13CONTROLLERS_A)($2) # --- Some other instructions $BB0_5: andi $1, $2, 1 ``` `lbu` got moved into the branch delay slot but has a load delay slot - so when jumping to `$BB0_5` the value for `$2` will not be ready, which leads to undefined behavior. This PR suggests to declare instructions with a load delay slot to be hazardous for the branch delay slot, only for `MIPS1`. This will prevent the load instructions in the branch delay slot, which has a slight impact on the optimization. Ideally in case of a load instruction in a branch delay slot, we would want to check the target register and check if it is used in the following instruction and at the branch destination instruction. Code for this is already in place from a previous PR (`bool MipsInstrInfo::SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const`), however I'm not experienced enough with the LLVM to identify the `MachineInstr` required for that ideal situation. If I could get some feedback about this I might be able to stitch it in. The original issue came from Rust and is described [here rust issue 150676](https://github.com/rust-lang/rust/issues/150676). It was then raised in the LLVM project [here issue 180639](https://github.com/llvm/llvm-project/issues/180639#issuecomment-3874380424) and in the forum [here](https://discourse.llvm.org/t/where-to-start-fixing-an-opt-pass-for-mips1/89857). Co-authored-by: Jaby <jaby@william.zone>
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