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llvm-project/llvm/test/CodeGen/Thumb2
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David Green 778b3b501f [ARM][MVE] Change MVE getSetCCResultType to always use i1 vectors (#192531) 
This mirrors what SVE does on the AArch64 side, where because we have
predicate vectors we can use them fall all types, and let legalization handle
where it is not the case. This fixes a clmul expansion that was failing to lower
the resulting intrinsic.
2026-04-28 19:19:10 +01:00
..
LowOverheadLoops
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
2026-04-17 12:23:56 +01:00
mve-intrinsics
[ARM] Fix duplicate RUN lines in tests (#182280)
2026-02-19 23:48:22 +00:00
2009-07-17-CrossRegClassCopy.ll
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2009-07-21-ISelBug.ll
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2009-07-23-CPIslandBug.ll
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2009-07-30-PEICrash.ll
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2009-08-01-WrongLDRBOpc.ll
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2009-08-02-CoalescerBug.ll
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2009-08-04-CoalescerAssert.ll
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2009-08-04-CoalescerBug.ll
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2009-08-04-ScavengerAssert.ll
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2009-08-04-SubregLoweringBug2.ll
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2009-08-04-SubregLoweringBug3.ll
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2009-08-04-SubregLoweringBug.ll
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2009-08-06-SpDecBug.ll
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2009-08-07-CoalescerBug.ll
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2009-08-07-NeonFPBug.ll
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2009-08-08-ScavengerAssert.ll
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2009-08-10-ISelBug.ll
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2009-08-21-PostRAKill4.ll
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2009-09-01-PostRAProlog.ll
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2009-10-15-ITBlockBranch.ll
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2009-11-01-CopyReg2RegBug.ll
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2009-11-11-ScavengerAssert.ll
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2009-11-13-STRDBug.ll
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2009-12-01-LoopIVUsers.ll
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2010-01-06-TailDuplicateLabels.ll
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2010-01-19-RemovePredicates.ll
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2010-02-11-phi-cycle.ll
[CodeGen] Do not remove IMPLICIT_DEF unless all uses have undef flag added (#188133)
2026-04-01 10:11:42 -05:00
2010-02-24-BigStack.ll
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2010-03-08-addi12-ccout.ll
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2010-03-15-AsmCCClobber.ll
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2010-04-15-DynAllocBug.ll
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2010-04-26-CopyRegCrash.ll
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2010-05-24-rsbs.ll
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2010-06-14-NEONCoalescer.ll
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2010-06-19-ITBlockCrash.ll
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2010-06-21-TailMergeBug.ll
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2010-08-10-VarSizedAllocaBug.ll
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2010-11-22-EpilogueBug.ll
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2010-12-03-AddSPNarrowing.ll
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2011-04-21-FILoweringBug.ll
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2011-06-07-TwoAddrEarlyClobber.ll
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2011-12-16-T2SizeReduceAssert.ll
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2012-01-13-CBNZBug.ll
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2013-02-19-tail-call-register-hint.ll
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2013-03-02-vduplane-nonconstant-source-index.ll
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2013-03-06-vector-sext-operand-scalarize.ll
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aapcs.ll
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abds-crash.ll
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abs.ll
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active_lane_mask.ll
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aligned-constants.ll
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aligned-nonfallthrough.ll
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aligned-spill.ll
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arm_canberra_distance_f32.ll
[AArch64][ARM] Add some tests for fcmp or branches. NFC
2026-02-11 07:55:32 +00:00
avoidmuls.mir
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bf16-instructions.ll
[ARM][AArch64] Replace ".f16(bfloat" with ".bf16(bfloat" in intrinsics. NFC
2025-12-14 04:39:41 +00:00
bf16-pcs.ll
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bfi.ll
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bfx.ll
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bicbfi.ll
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bti-entry-blocks.ll
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bti-indirect-branches.ll
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bti-jump-table.mir
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bti-outliner-1.ll
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bti-outliner-2.ll
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bti-outliner-cost-1.ll
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bti-outliner-cost-2.ll
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bti-pac-replace-1.mir
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bti-pac-replace-2.ll
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bug-subw.ll
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buildvector-crash.ll
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call-site-info-update.ll
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carry.ll
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cbnz.ll
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cde-gpr.ll
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cde-vec.ll
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cde-vfp.ll
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cmp-frame.ll
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cmpxchg.mir
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constant-hoisting.ll
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constant-islands-cbz.ll
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constant-islands-cbz.mir
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constant-islands-cbzundef.mir
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constant-islands-jump-table.ll
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constant-islands-ldrsb.mir
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constant-islands-new-island-padding.ll
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constant-islands-new-island.ll
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constant-islands.ll
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cortex-fp.ll
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crash.ll
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cross-rc-coalescing-1.ll
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cross-rc-coalescing-2.ll
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csel-andor-onebit.ll
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csel.ll
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div.ll
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emit-unwinding.ll
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expand-pseudos.mir
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fir.ll
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float-cmp.ll
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float-intrinsics-double.ll
IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)
2026-01-21 09:50:28 +00:00
float-intrinsics-float.ll
IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)
2026-01-21 09:50:28 +00:00
float-ops.ll
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fp16-pcs.ll
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fp16-stacksplot.mir
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frame-index-addrmode-t2i8s4.mir
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frame-pointer.ll
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frameless2.ll
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frameless.ll
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high-reg-spill.mir
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
2026-04-17 12:23:56 +01:00
ifcvt-cbz.mir
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ifcvt-compare.ll
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ifcvt-dead-predicate.mir
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ifcvt-minsize.ll
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ifcvt-neon-deprecated.mir
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ifcvt-no-branch-predictor.ll
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ifcvt-rescan-bug-2016-08-22.ll
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ifcvt-rescan-diamonds.ll
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indirect-tail-call-free-registers.ll
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inflate-regs.ll
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inline-asm-i-constraint-i1.ll
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inlineasm-error-t-toofewregs-mve.ll
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inlineasm-mve.ll
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inlineasm.ll
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intrinsics-cc.ll
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intrinsics-coprocessor.ll
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jump-table-bti.ll
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large-call.ll
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large-stack.ll
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ldr-str-imm12.ll
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lit.local.cfg
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longMACt.ll
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lsll0.ll
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lsr-deficiency.ll
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m4-sched-ldr.mir
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m4-sched-regs.ll
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machine-licm.ll
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mul_const.ll
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mve-abs.ll
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mve-basic.ll
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mve-be.ll
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mve-bitarith.ll
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mve-bitcasts.ll
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mve-bitreverse.ll
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mve-blockplacement.ll
[LSR] Insert the transformed IV increment in the user block (#169515)
2025-12-02 17:15:00 +00:00
mve-bswap.ll
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mve-clmul.ll
[ARM][MVE] Change MVE getSetCCResultType to always use i1 vectors (#192531)
2026-04-28 19:19:10 +01:00
mve-complex-deinterleaving-f16-add.ll
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mve-complex-deinterleaving-f16-mul.ll
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mve-complex-deinterleaving-f32-add.ll
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mve-complex-deinterleaving-f32-mul.ll
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mve-complex-deinterleaving-f64-add.ll
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mve-complex-deinterleaving-f64-mul.ll
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mve-complex-deinterleaving-i8-add.ll
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mve-complex-deinterleaving-i16-add.ll
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mve-complex-deinterleaving-i32-add.ll
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mve-complex-deinterleaving-i64-add.ll
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mve-complex-deinterleaving-mixed-cases.ll
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mve-complex-deinterleaving-uniform-cases.ll
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mve-concat.ll
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mve-ctlz.ll
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mve-ctpop.ll
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mve-cttz.ll
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mve-div-expand.ll
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mve-doublereduct.ll
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mve-extbuildvec.ll
[ARM][MVE] Transform sext and zext of i1 buildvector (#192519)
2026-04-25 13:47:46 +00:00
mve-extractelt.ll
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mve-extractstore.ll
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mve-fastcc.ll
[ARM] Use FPRegs for fastcc calling convention detection. (#184593)
2026-03-11 13:52:56 +00:00
mve-float16regloops.ll
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mve-float32regloops.ll
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mve-fma-loops.ll
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mve-fmas.ll
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mve-fmath.ll
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mve-fp16convertloops.ll
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mve-fp-negabs.ll
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mve-fpclamptosat_vec.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
mve-fptosi-sat-vector.ll
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mve-fptoui-sat-vector.ll
[SelectionDAG] Fix fptoui.sat expansion using minnum/maxnum (#180178)
2026-02-25 12:23:42 +00:00
mve-frint.ll
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mve-gather-increment.ll
[MVEGatherScatter] Fix GEP scale calculations (#185437)
2026-03-09 16:58:35 +01:00
mve-gather-ind8-unscaled.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
mve-gather-ind16-scaled.ll
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mve-gather-ind16-unscaled.ll
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mve-gather-ind32-scaled.ll
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mve-gather-ind32-unscaled.ll
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mve-gather-optimisation-deep.ll
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mve-gather-ptrs.ll
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mve-gather-scatter-opt.ll
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mve-gather-scatter-optimisation.ll
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mve-gather-scatter-ptr-address.ll
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mve-gather-scatter-tailpred.ll
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mve-gather-tailpred.ll
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mve-gather-unused.ll
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mve-gatherscatter-mmo.ll
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mve-halving.ll
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mve-insertshuffleload.ll
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mve-laneinterleaving-cost.ll
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mve-laneinterleaving-reduct.ll
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mve-laneinterleaving.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
mve-ldst-offset.ll
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mve-ldst-postinc.ll
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mve-ldst-preinc.ll
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mve-ldst-regimm.ll
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mve-loadstore.ll
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mve-masked-ldst-offset.ll
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mve-masked-ldst-postinc.ll
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mve-masked-ldst-preinc.ll
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mve-masked-ldst.ll
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mve-masked-load.ll
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mve-masked-store-mmo.ll
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mve-masked-store.ll
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mve-memtp-branch.ll
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mve-memtp-loop.ll
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mve-minmax.ll
[AArch64][Thumb2] Add missing select FMF in tests
2026-03-06 15:37:03 +01:00
mve-minmaxi.ll
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mve-multivec-spill.ll
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mve-neg.ll
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mve-no-fp.ll
arm: fix float to integer conversion with +mve (#193319)
2026-04-22 16:29:48 +02:00
mve-nofloat.ll
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mve-nounrolledremainder.ll
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mve-phireg.ll
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mve-pipelineloops.ll
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mve-postinc-dct.ll
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mve-postinc-distribute.ll
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mve-postinc-distribute.mir
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mve-postinc-lsr.ll
[CodeGen] Treat hasOrderedMemoryRef as implying arbitrary loads or stores (#182000)
2026-03-04 17:49:11 +00:00
mve-pred-and.ll
[DAGCombine] Optimize away cond ? 1 : 0 post-legalization (#186771)
2026-03-20 16:23:18 +01:00
mve-pred-bitcast.ll
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mve-pred-build-const.ll
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mve-pred-build-var.ll
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mve-pred-const.ll
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mve-pred-constfold.ll
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mve-pred-constfold.mir
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mve-pred-convert.ll
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mve-pred-ext.ll
[ARM][MVE] Change MVE getSetCCResultType to always use i1 vectors (#192531)
2026-04-28 19:19:10 +01:00
mve-pred-loadstore.ll
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mve-pred-not.ll
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mve-pred-or.ll
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mve-pred-selectop2.ll
[AArch64][Thumb2] Add missing select FMF in tests
2026-03-06 15:37:03 +01:00
mve-pred-selectop3.ll
[AArch64][Thumb2] Add missing select FMF in tests
2026-03-06 15:37:03 +01:00
mve-pred-selectop.ll
[AArch64][Thumb2] Add missing select FMF in tests
2026-03-06 15:37:03 +01:00
mve-pred-shuffle.ll
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mve-pred-spill.ll
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mve-pred-threshold.ll
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mve-pred-vctpvpsel.ll
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mve-pred-vselect.ll
[DAGCombine] Optimize away cond ? 1 : 0 post-legalization (#186771)
2026-03-20 16:23:18 +01:00
mve-pred-xor.ll
[DAGCombine] Optimize away cond ? 1 : 0 post-legalization (#186771)
2026-03-20 16:23:18 +01:00
mve-qrintr.ll
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mve-qrintrsplat.ll
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mve-satmul-loops.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
mve-saturating-arith.ll
[SelectionDAG] Change SSUBO to do (LHS < RHS) XOR (RESULT < 0) (#191747)
2026-04-22 18:03:33 +01:00
mve-scatter-increment.ll
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mve-scatter-ind8-unscaled.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
mve-scatter-ind16-scaled.ll
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mve-scatter-ind16-unscaled.ll
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mve-scatter-ind32-scaled.ll
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mve-scatter-ind32-unscaled.ll
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mve-scatter-ptrs.ll
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mve-scmp.ll
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mve-selectcc.ll
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mve-sext-masked-load.ll
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mve-sext.ll
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mve-shifts-scalar.ll
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mve-shifts.ll
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mve-shuffle.ll
[Thumb2] mve-shuffle.ll - add missing check prefix coverage for some fullfp16 cases (#180567)
2026-02-10 13:37:24 +00:00
mve-shuffleext.ll
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mve-shufflemov.ll
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mve-simple-arith.ll
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mve-sli-sri.ll
[ARM][MVE] Add SLI and SRI recognition. (#183471)
2026-02-28 10:43:42 +00:00
mve-soft-float-abi.ll
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mve-stack.ll
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mve-stacksplot.mir
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mve-strict-round.ll
[ARM] Treat strictfp vector rounding operations as legal (#180480)
2026-02-20 12:37:10 +07:00
mve-tailpred-loopinvariant.ll
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mve-tailpred-nonzerostart.ll
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mve-tailpred-vptblock.ll
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mve-tp-loop.mir
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mve-ucmp.ll
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mve-useafterloop.ll
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mve-vabd.ll
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mve-vabdus.ll
[SDAG] (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??) (#175459)
2026-01-13 17:00:00 +00:00
mve-vadc-vsbc-spill.ll
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mve-vaddqr.ll
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mve-vaddv.ll
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mve-vcmla.ll
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mve-vcmp.ll
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mve-vcmpf.ll
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mve-vcmpfr.ll
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mve-vcmpfz.ll
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mve-vcmpr.ll
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mve-vcmpz.ll
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mve-vcreate.ll
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mve-vctp.ll
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mve-vcvt16.ll
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mve-vcvt-fixed-to-float.ll
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mve-vcvt-float-to-fixed.ll
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mve-vcvt.ll
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mve-vdup.ll
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mve-vecreduce-add-combine.ll
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mve-vecreduce-add.ll
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mve-vecreduce-addpred.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
mve-vecreduce-bit.ll
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mve-vecreduce-fadd.ll
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mve-vecreduce-fminmax.ll
[AArch64][Thumb2] Add missing select FMF in tests
2026-03-06 15:37:03 +01:00
mve-vecreduce-fmul.ll
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mve-vecreduce-loops.ll
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mve-vecreduce-mla.ll
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mve-vecreduce-mlapred.ll
[SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
2026-02-23 14:38:07 +01:00
mve-vecreduce-mul.ll
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mve-vecreduce-slp.ll
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mve-vector-spill.ll
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mve-vfma.ll
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mve-vhadd.ll
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mve-vhaddsub.ll
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mve-vidup.ll
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mve-vld2-post.ll
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mve-vld2.ll
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mve-vld3.ll
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mve-vld4-post.ll
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mve-vld4.ll
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mve-vldshuffle.ll
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mve-vldst4.ll
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mve-vmaxnma-commute.ll
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mve-vmaxnma-tailpred.ll
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mve-vmaxv-vminv-scalar.ll
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mve-vmaxv.ll
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mve-vmla.ll
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mve-vmovimm.ll
[Thumb2] mve-vmovimm.ll - regenerate with missing check prefixes (#183019)
2026-02-24 10:20:58 +00:00
mve-vmovlloop.ll
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mve-vmovn.ll
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mve-vmovnstore.ll
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mve-vmulh.ll
[DAG] Use known-bits when creating umulh/smulh. (#160916)
2026-04-07 19:12:15 +01:00
mve-vmull-loop.ll
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mve-vmull-splat.ll
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mve-vmull.ll
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mve-vmulqr.ll
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mve-vmvnimm.ll
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mve-vpsel.ll
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mve-vpt-2-blocks-1-pred.mir
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
mve-vpt-2-blocks-2-preds.mir
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mve-vpt-2-blocks-ctrl-flow.mir
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mve-vpt-2-blocks-non-consecutive-ins.mir
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mve-vpt-2-blocks.mir
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mve-vpt-3-blocks-kill-vpr.mir
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mve-vpt-block-1-ins.mir
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mve-vpt-block-2-ins.mir
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mve-vpt-block-4-ins.mir
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mve-vpt-block-debug.mir
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mve-vpt-block-elses.mir
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mve-vpt-block-fold-vcmp.mir
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mve-vpt-block-kill.mir
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mve-vpt-block-optnone.mir
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mve-vpt-blocks.ll
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mve-vpt-from-intrinsics.ll
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mve-vpt-nots.mir
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mve-vpt-optimisations.mir
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mve-vpt-preuse.mir
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mve-vqdmulh-minmax.ll
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mve-vqdmulh.ll
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mve-vqmovn-combine.ll
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mve-vqmovn.ll
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mve-vqshrn.ll
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mve-vselect-constants.ll
[ARM] hasAndNot in ARM supports vectors (#193614)
2026-04-27 15:56:12 +01:00
mve-vst2-post.ll
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mve-vst2.ll
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mve-vst3.ll
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mve-vst4-post.ll
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mve-vst4.ll
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mve-vsubqr.ll
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mve-widen-narrow.ll
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mve-wls-block-placement.mir
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mve-zext-masked-load.ll
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outlined-fn-may-clobber-lr-in-caller.ll
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pacbti-m-basic.ll
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pacbti-m-bxaut.ll
[Thumb2] Use BXAUT instruction if available (#183056)
2026-03-03 16:37:43 +00:00
pacbti-m-frame-chain.ll
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pacbti-m-indirect-tail-call.ll
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pacbti-m-outliner-1.ll
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pacbti-m-outliner-2.ll
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pacbti-m-outliner-3.ll
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pacbti-m-outliner-4.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
pacbti-m-outliner-5.ll
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pacbti-m-overalign.ll
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pacbti-m-stack-arg.ll
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pacbti-m-unsupported-arch.ll
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pacbti-m-varargs-1.ll
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pacbti-m-varargs-2.ll
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pacbti-m-vla.ll
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peephole-addsub.mir
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peephole-cmp.mir
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peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
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phi_prevent_copy.mir
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pic-load.ll
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pipeliner-inlineasm.mir
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
2026-04-17 12:23:56 +01:00
pipeliner-preserve-ties.mir
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postinc-distribute.mir
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pr52817.ll
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scavenge-lr.mir
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schedm7-hazard.ll
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segmented-stacks.ll
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setjmp_longjmp.ll
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shift_parts.ll
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srem-seteq-illegal-types.ll
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stack_guard_remat.ll
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store-prepostinc.mir
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swp-exitbranchdir.mir
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swp-fixedii-le.mir
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swp-fixedii.mir
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swp-regpressure.mir
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t2-teq-reduce.mir
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t2peephole-t2ADDrr-to-t2ADDri.ll
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t2sizereduction.mir
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tail-call-r9.ll
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tbb-removeadd.mir
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thumb2-adc.ll
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thumb2-add2.ll
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thumb2-add3.ll
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thumb2-add4.ll
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thumb2-add5.ll
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thumb2-add6.ll
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thumb2-add.ll
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thumb2-and2.ll
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thumb2-and.ll
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thumb2-asr2.ll
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thumb2-asr.ll
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thumb2-bcc.ll
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thumb2-bfc.ll
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thumb2-bic.ll
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thumb2-branch.ll
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thumb2-call-tc.ll
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thumb2-call.ll
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thumb2-cbnz.ll
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thumb2-clz.ll
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thumb2-cmn2.ll
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thumb2-cmn.ll
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thumb2-cmp.ll
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thumb2-cpsr-liveness.ll
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thumb2-eor2.ll
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thumb2-eor.ll
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thumb2-execute-only-long-calls.ll
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thumb2-execute-only-prologue.ll
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thumb2-ifcvt1-tc.ll
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thumb2-ifcvt1.ll
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thumb2-ifcvt2.ll
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thumb2-ifcvt3.ll
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thumb2-jtb.ll
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thumb2-ldm.ll
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thumb2-ldr_ext.ll
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thumb2-ldr_post.ll
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thumb2-ldr_pre.ll
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thumb2-ldr.ll
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thumb2-ldrb.ll
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thumb2-ldrd.ll
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thumb2-ldrh.ll
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thumb2-lsl2.ll
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thumb2-lsl.ll
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thumb2-lsr2.ll
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thumb2-lsr3.ll
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thumb2-lsr.ll
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thumb2-mla.ll
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thumb2-mls.ll
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thumb2-mov.ll
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thumb2-mul.ll
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thumb2-mulhi.ll
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thumb2-mvn2.ll
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thumb2-mvn.ll
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thumb2-neg.ll
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thumb2-orn2.ll
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thumb2-orn.ll
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thumb2-orr2.ll
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thumb2-orr.ll
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thumb2-pack.ll
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thumb2-rev16.ll
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thumb2-rev.ll
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thumb2-ror.ll
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thumb2-rsb2.ll
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thumb2-rsb.ll
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thumb2-sbc.ll
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thumb2-select_xform.ll
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thumb2-select.ll
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thumb2-shifter.ll
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thumb2-smla.ll
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thumb2-smul.ll
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thumb2-spill-q.ll
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thumb2-str_post.ll
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thumb2-str_pre.ll
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thumb2-str.ll
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thumb2-strb.ll
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thumb2-strh.ll
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thumb2-sub2.ll
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thumb2-sub3.ll
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thumb2-sub4.ll
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thumb2-sub5.ll
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thumb2-sub.ll
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thumb2-sxt_rot.ll
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thumb2-sxt-uxt.ll
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thumb2-tbb.ll
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thumb2-tbh.ll
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thumb2-teq2.ll
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thumb2-teq.ll
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thumb2-tst2.ll
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thumb2-tst.ll
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thumb2-uxt_rot.ll
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thumb2-uxtb.ll
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tls1.ll
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tls2.ll
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tpsoft.ll
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umulo-64-legalisation-lowering.ll
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umulo-128-legalisation-lowering.ll
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unreachable-large-offset-gep.ll
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urem-seteq-illegal-types.ll
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v8_IT_1.ll
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v8_IT_2.ll
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v8_IT_3.ll
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v8_IT_4.ll
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v8_IT_5.ll
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v8_IT_6.ll
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vmovdrroffset.ll
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vqabs.ll
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vqneg.ll
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