58df9b1a01
This block of code is currently conditional on the fusions being enabled but as far as I can tell, does no harm to generally enable. The net effect is the generically compiled code runs slightly better on machines with this fusion. The actual motivation is merely to stop confusing myself when I see the sequence in code; the register allocators choice to sometimes blow two registers instead of one is just generally weird, and my eyes spot it when scanning disassembly. (Note that this is just the regalloc hint; the scheduling changes remain conditional, and probably should remain so.)
57 lines
2.0 KiB
LLVM
57 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv32 -mattr=+zcmp,+e -target-abi ilp32e -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
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declare i32 @__mulsi3(i32, i32)
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define ptr @func(ptr %s, i32 %_c, ptr %incdec.ptr, i1 %0, i8 %conv14) #0 {
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; RV32-LABEL: func:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: cm.push {ra, s0-s1}, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: .cfi_offset ra, -12
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: .cfi_offset s1, -4
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; RV32-NEXT: addi sp, sp, -8
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; RV32-NEXT: .cfi_def_cfa_offset 24
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; RV32-NEXT: sw a4, 4(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw a2, 0(sp) # 4-byte Folded Spill
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; RV32-NEXT: mv a2, a1
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; RV32-NEXT: mv s1, a0
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; RV32-NEXT: li a0, 1
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; RV32-NEXT: andi a3, a3, 1
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; RV32-NEXT: .LBB0_1: # %while.body
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: mv s0, a0
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: bnez a3, .LBB0_1
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; RV32-NEXT: # %bb.2: # %while.end
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; RV32-NEXT: lui a1, 4112
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; RV32-NEXT: addi a1, a1, 257
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; RV32-NEXT: mv a0, a2
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; RV32-NEXT: call __mulsi3
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; RV32-NEXT: sw a0, 0(zero)
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; RV32-NEXT: andi s0, s0, 1
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; RV32-NEXT: lw a0, 0(sp) # 4-byte Folded Reload
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; RV32-NEXT: add s0, s0, a0
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; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
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; RV32-NEXT: sb a0, 0(s0)
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; RV32-NEXT: mv a0, s1
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; RV32-NEXT: addi sp, sp, 8
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: cm.popret {ra, s0-s1}, 16
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entry:
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br label %while.body
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while.body: ; preds = %while.body, %entry
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%n.addr.042 = phi i32 [ 1, %entry ], [ 0, %while.body ]
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br i1 %0, label %while.body, label %while.end
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while.end: ; preds = %while.body
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%mul_result = call i32 @__mulsi3(i32 %_c, i32 16843009)
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store i32 %mul_result, ptr null, align 4
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%1 = and i32 %n.addr.042, 1
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%scevgep = getelementptr i8, ptr %incdec.ptr, i32 %1
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store i8 %conv14, ptr %scevgep, align 1
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ret ptr %s
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}
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