e95f6fa123
Introduce a target hook to incrementally flip the behavior of targets with test changes, and start by implementing it for AMDGPU. This appears to be forgotten switch flip from 2015. This seems to do a nicer job with subregister copies. Most of the test changes are improvements or neutral, not that many are light regressions. The worst AMDGPU regressions are for true16 in the atomic tests, but I think that's due to existing true16 issues.
239 lines
8.1 KiB
LLVM
239 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=GCN
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define amdgpu_ps float @while_break(i32 %z, float %v, i32 %x, i32 %y) #0 {
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; GCN-LABEL: while_break:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_mov_b32 s1, -1
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; GCN-NEXT: s_mov_b32 s0, 0
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; GCN-NEXT: s_branch .LBB0_2
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; GCN-NEXT: .LBB0_1: ; %Flow2
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_and_b32 s2, exec_lo, s3
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; GCN-NEXT: s_or_b32 s0, s2, s0
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; GCN-NEXT: s_andn2_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: s_cbranch_execz .LBB0_8
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; GCN-NEXT: .LBB0_2: ; %header
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_add_i32 s1, s1, 1
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, s1, v2
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; GCN-NEXT: s_and_saveexec_b32 s3, vcc_lo
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; GCN-NEXT: s_xor_b32 s3, exec_lo, s3
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; GCN-NEXT: ; %bb.3: ; %else
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v3
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; GCN-NEXT: s_and_b32 s2, vcc_lo, exec_lo
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; GCN-NEXT: ; %bb.4: ; %Flow
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_andn2_saveexec_b32 s3, s3
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; GCN-NEXT: ; %bb.5: ; %if
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: s_or_b32 s2, s2, exec_lo
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; GCN-NEXT: ; %bb.6: ; %Flow1
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; GCN-NEXT: s_mov_b32 s3, -1
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; GCN-NEXT: s_and_saveexec_b32 s4, s2
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; GCN-NEXT: s_cbranch_execz .LBB0_1
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; GCN-NEXT: ; %bb.7: ; %latch
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v0
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; GCN-NEXT: s_orn2_b32 s3, vcc_lo, exec_lo
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; GCN-NEXT: s_branch .LBB0_1
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; GCN-NEXT: .LBB0_8: ; %end
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: ; return to shader part epilog
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entry:
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br label %header
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header:
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%v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]
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%ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]
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%cc = icmp slt i32 %ind, %x
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br i1 %cc, label %if, label %else
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if:
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%v.if = fadd float %v.1, 1.0
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br label %latch
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else:
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%cc2 = icmp slt i32 %ind, %y
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br i1 %cc2, label %latch, label %end
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latch:
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%v.2 = phi float [ %v.if, %if ], [ %v.1, %else ]
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%ind.inc = add i32 %ind, 1
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%cc3 = icmp slt i32 %ind, %z
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br i1 %cc3, label %end, label %header
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end:
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%r = phi float [ %v.2, %latch ], [ %v.1, %else ]
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ret float %r
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}
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; Just different dfs order from while_break.
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define amdgpu_ps float @while_break2(i32 %z, float %v, i32 %x, i32 %y) #0 {
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; GCN-LABEL: while_break2:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_mov_b32 s1, -1
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; GCN-NEXT: s_mov_b32 s0, 0
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; GCN-NEXT: s_branch .LBB1_2
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; GCN-NEXT: .LBB1_1: ; %Flow2
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_and_b32 s2, exec_lo, s3
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; GCN-NEXT: s_or_b32 s0, s2, s0
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; GCN-NEXT: s_andn2_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: s_cbranch_execz .LBB1_8
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; GCN-NEXT: .LBB1_2: ; %header
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_add_i32 s1, s1, 1
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, s1, v2
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; GCN-NEXT: s_and_saveexec_b32 s3, vcc_lo
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; GCN-NEXT: s_xor_b32 s3, exec_lo, s3
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; GCN-NEXT: ; %bb.3: ; %if
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: s_mov_b32 s2, exec_lo
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; GCN-NEXT: ; %bb.4: ; %Flow
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_andn2_saveexec_b32 s3, s3
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; GCN-NEXT: ; %bb.5: ; %else
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v3
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; GCN-NEXT: s_andn2_b32 s2, s2, exec_lo
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; GCN-NEXT: s_and_b32 s4, vcc_lo, exec_lo
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; GCN-NEXT: s_or_b32 s2, s2, s4
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; GCN-NEXT: ; %bb.6: ; %Flow1
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; GCN-NEXT: s_mov_b32 s3, -1
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; GCN-NEXT: s_and_saveexec_b32 s4, s2
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; GCN-NEXT: s_cbranch_execz .LBB1_1
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; GCN-NEXT: ; %bb.7: ; %latch
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v0
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; GCN-NEXT: s_orn2_b32 s3, vcc_lo, exec_lo
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; GCN-NEXT: s_branch .LBB1_1
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; GCN-NEXT: .LBB1_8: ; %end
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: ; return to shader part epilog
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entry:
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br label %header
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header:
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%v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]
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%ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]
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%cc = icmp slt i32 %ind, %x
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br i1 %cc, label %else, label %if
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if:
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%v.if = fadd float %v.1, 1.0
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br label %latch
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else:
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%cc2 = icmp slt i32 %ind, %y
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br i1 %cc2, label %latch, label %end
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latch:
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%v.2 = phi float [ %v.if, %if ], [ %v.1, %else ]
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%ind.inc = add i32 %ind, 1
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%cc3 = icmp slt i32 %ind, %z
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br i1 %cc3, label %end, label %header
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end:
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%r = phi float [ %v.2, %latch ], [ %v.1, %else ]
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ret float %r
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}
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; Two chains of phi network that have the same value from %if block.
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define amdgpu_ps < 2 x float> @while_break_two_chains_of_phi(float %v, i32 %x, i32 %y, i32 %z, ptr addrspace(1) %p) #0 {
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; GCN-LABEL: while_break_two_chains_of_phi:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_mov_b32_e32 v6, 0
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; GCN-NEXT: s_mov_b32 s0, 0
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: s_branch .LBB2_2
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; GCN-NEXT: .LBB2_1: ; %Flow1
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; GCN-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_and_b32 s1, exec_lo, s1
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; GCN-NEXT: s_or_b32 s2, s1, s2
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; GCN-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
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; GCN-NEXT: s_cbranch_execz .LBB2_6
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; GCN-NEXT: .LBB2_2: ; %header
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: v_cmp_ge_i32_e64 s3, s0, v1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s0, v1
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; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; GCN-NEXT: s_cbranch_execz .LBB2_4
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; GCN-NEXT: ; %bb.3: ; %if
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; GCN-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GCN-NEXT: s_ashr_i32 s1, s0, 31
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; GCN-NEXT: s_lshl_b64 s[6:7], s[0:1], 2
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; GCN-NEXT: s_andn2_b32 s1, s3, exec_lo
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; GCN-NEXT: v_add_co_u32 v6, vcc_lo, v4, s6
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; GCN-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s0, v2
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; GCN-NEXT: global_load_dword v0, v[6:7], off
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; GCN-NEXT: s_and_b32 s3, vcc_lo, exec_lo
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; GCN-NEXT: s_or_b32 s3, s1, s3
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v6, 1.0, v0
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; GCN-NEXT: v_mov_b32_e32 v0, v6
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; GCN-NEXT: .LBB2_4: ; %Flow
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; GCN-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_mov_b32 s1, -1
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; GCN-NEXT: s_and_saveexec_b32 s4, s3
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; GCN-NEXT: s_cbranch_execz .LBB2_1
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; GCN-NEXT: ; %bb.5: ; %latch
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; GCN-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s0, v3
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; GCN-NEXT: s_add_i32 s0, s0, 1
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; GCN-NEXT: s_orn2_b32 s1, vcc_lo, exec_lo
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; GCN-NEXT: s_branch .LBB2_1
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; GCN-NEXT: .LBB2_6: ; %end
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s2
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; GCN-NEXT: v_mov_b32_e32 v1, v6
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; GCN-NEXT: ; return to shader part epilog
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entry:
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br label %header
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header:
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%v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]
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%v.copy = phi float [ 0.0, %entry ], [ %v.copy.2, %latch ]
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%ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]
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%cc = icmp slt i32 %ind, %x
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br i1 %cc, label %if, label %latch
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if:
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%v.ptr = getelementptr float, ptr addrspace(1) %p, i32 %ind
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%v.load = load float, ptr addrspace(1) %v.ptr
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%v.if = fadd float %v.load, 1.0
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%cc2 = icmp slt i32 %ind, %y
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br i1 %cc2, label %latch, label %end
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latch:
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%v.2 = phi float [ %v.1, %header ], [ %v.if, %if ]
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%v.copy.2 = phi float [ %v.copy, %header ], [ %v.if, %if ]
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%ind.inc = add i32 %ind, 1
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%cc3 = icmp slt i32 %ind, %z
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br i1 %cc3, label %end, label %header
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end:
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%r = phi float [ %v.2, %latch ], [ %v.if, %if ]
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%r2 = phi float [ %v.copy.2, %latch ], [ %v.if, %if ]
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%packed0 = insertelement < 2 x float > poison, float %r, i32 0
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%packed1 = insertelement < 2 x float > %packed0, float %r2, i32 1
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ret < 2 x float> %packed1
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}
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attributes #0 = { nounwind }
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