16897c234a
Moves Wasm GISel to use the the new extended LLTs added by #155107. Extended LLTs have (optional) information about whether a particular scalar is integer vs floating-point. This is a big win for Wasm, since we can avoid a lot of guess work, and map LLT i32, i64, f32, and f64 directly to their Wasm counterparts. To take full advantage of this, RegBankSelect has been automated, iterating over all operands and mapping typed LLTs to their appropriate register bank.
741 lines
28 KiB
C++
741 lines
28 KiB
C++
//===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the WebAssembly-specific subclass of TargetMachine.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyTargetMachine.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "TargetInfo/WebAssemblyTargetInfo.h"
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#include "WebAssembly.h"
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#include "WebAssemblyISelLowering.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblyTargetObjectFile.h"
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#include "WebAssemblyTargetTransformInfo.h"
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#include "WebAssemblyUtilities.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/MIRParser/MIParser.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Function.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/Scalar/LowerAtomicPass.h"
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#include "llvm/Transforms/Utils.h"
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#include <optional>
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using namespace llvm;
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#define DEBUG_TYPE "wasm"
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// A command-line option to keep implicit locals
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// for the purpose of testing with lit/llc ONLY.
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// This produces output which is not valid WebAssembly, and is not supported
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// by assemblers/disassemblers and other MC based tools.
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static cl::opt<bool> WasmDisableExplicitLocals(
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"wasm-disable-explicit-locals", cl::Hidden,
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cl::desc("WebAssembly: output implicit locals in"
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" instruction output for test purposes only."),
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cl::init(false));
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// Exception handling & setjmp-longjmp handling related options.
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// Emscripten's asm.js-style exception handling
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cl::opt<bool> WebAssembly::WasmEnableEmEH(
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"enable-emscripten-cxx-exceptions",
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cl::desc("WebAssembly Emscripten-style exception handling"),
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cl::init(false));
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// Emscripten's asm.js-style setjmp/longjmp handling
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cl::opt<bool> WebAssembly::WasmEnableEmSjLj(
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"enable-emscripten-sjlj",
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cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
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cl::init(false));
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// Exception handling using wasm EH instructions
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cl::opt<bool>
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WebAssembly::WasmEnableEH("wasm-enable-eh",
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cl::desc("WebAssembly exception handling"));
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// setjmp/longjmp handling using wasm EH instrutions
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cl::opt<bool> WebAssembly::WasmEnableSjLj(
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"wasm-enable-sjlj", cl::desc("WebAssembly setjmp/longjmp handling"));
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// If true, use the legacy Wasm EH proposal:
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// https://github.com/WebAssembly/exception-handling/blob/main/proposals/exception-handling/legacy/Exceptions.md
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// And if false, use the standardized Wasm EH proposal:
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// https://github.com/WebAssembly/exception-handling/blob/main/proposals/exception-handling/Exceptions.md
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// Currently set to true by default because not all major web browsers turn on
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// the new standard proposal by default, but will later change to false.
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cl::opt<bool> WebAssembly::WasmUseLegacyEH(
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"wasm-use-legacy-eh", cl::desc("WebAssembly exception handling (legacy)"),
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cl::init(true));
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extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
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LLVMInitializeWebAssemblyTarget() {
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// Register the target.
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RegisterTargetMachine<WebAssemblyTargetMachine> X(
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getTheWebAssemblyTarget32());
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RegisterTargetMachine<WebAssemblyTargetMachine> Y(
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getTheWebAssemblyTarget64());
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// Register backend passes
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auto &PR = *PassRegistry::getPassRegistry();
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initializeGlobalISel(PR);
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initializeWebAssemblyPreLegalizerCombinerPass(PR);
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initializeWebAssemblyPostLegalizerCombinerPass(PR);
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initializeWebAssemblyAddMissingPrototypesPass(PR);
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initializeWebAssemblyLowerEmscriptenEHSjLjPass(PR);
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initializeLowerGlobalDtorsLegacyPassPass(PR);
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initializeFixFunctionBitcastsPass(PR);
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initializeOptimizeReturnedPass(PR);
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initializeWebAssemblyRefTypeMem2LocalPass(PR);
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initializeWebAssemblyArgumentMovePass(PR);
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initializeWebAssemblyAsmPrinterPass(PR);
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initializeWebAssemblySetP2AlignOperandsPass(PR);
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initializeWebAssemblyReplacePhysRegsPass(PR);
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initializeWebAssemblyOptimizeLiveIntervalsPass(PR);
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initializeWebAssemblyMemIntrinsicResultsPass(PR);
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initializeWebAssemblyRegStackifyPass(PR);
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initializeWebAssemblyRegColoringPass(PR);
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initializeWebAssemblyNullifyDebugValueListsPass(PR);
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initializeWebAssemblyFixIrreducibleControlFlowPass(PR);
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initializeWebAssemblyLateEHPreparePass(PR);
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initializeWebAssemblyExceptionInfoPass(PR);
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initializeWebAssemblyCFGSortPass(PR);
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initializeWebAssemblyCFGStackifyPass(PR);
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initializeWebAssemblyExplicitLocalsPass(PR);
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initializeWebAssemblyLowerBrUnlessPass(PR);
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initializeWebAssemblyRegNumberingPass(PR);
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initializeWebAssemblyDebugFixupPass(PR);
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initializeWebAssemblyPeepholePass(PR);
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initializeWebAssemblyMCLowerPrePassPass(PR);
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initializeWebAssemblyLowerRefTypesIntPtrConvPass(PR);
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initializeWebAssemblyFixBrTableDefaultsPass(PR);
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initializeWebAssemblyDAGToDAGISelLegacyPass(PR);
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}
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//===----------------------------------------------------------------------===//
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// WebAssembly Lowering public interface.
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//===----------------------------------------------------------------------===//
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static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
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// Default to static relocation model. This should always be more optimial
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// than PIC since the static linker can determine all global addresses and
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// assume direct function calls.
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return RM.value_or(Reloc::Static);
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}
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using WebAssembly::WasmEnableEH;
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using WebAssembly::WasmEnableEmEH;
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using WebAssembly::WasmEnableEmSjLj;
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using WebAssembly::WasmEnableSjLj;
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static void basicCheckForEHAndSjLj(TargetMachine *TM) {
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// You can't enable two modes of EH at the same time
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if (WasmEnableEmEH && WasmEnableEH)
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report_fatal_error(
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"-enable-emscripten-cxx-exceptions not allowed with -wasm-enable-eh");
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// You can't enable two modes of SjLj at the same time
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if (WasmEnableEmSjLj && WasmEnableSjLj)
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report_fatal_error(
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"-enable-emscripten-sjlj not allowed with -wasm-enable-sjlj");
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// You can't mix Emscripten EH with Wasm SjLj.
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if (WasmEnableEmEH && WasmEnableSjLj)
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report_fatal_error(
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"-enable-emscripten-cxx-exceptions not allowed with -wasm-enable-sjlj");
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if (TM->Options.ExceptionModel == ExceptionHandling::None) {
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// FIXME: These flags should be removed in favor of directly using the
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// generically configured ExceptionsType
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if (WebAssembly::WasmEnableEH || WebAssembly::WasmEnableSjLj)
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TM->Options.ExceptionModel = ExceptionHandling::Wasm;
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}
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// Basic Correctness checking related to -exception-model
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if (TM->Options.ExceptionModel != ExceptionHandling::None &&
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TM->Options.ExceptionModel != ExceptionHandling::Wasm)
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report_fatal_error("-exception-model should be either 'none' or 'wasm'");
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if (WasmEnableEmEH && TM->Options.ExceptionModel == ExceptionHandling::Wasm)
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report_fatal_error("-exception-model=wasm not allowed with "
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"-enable-emscripten-cxx-exceptions");
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if (WasmEnableEH && TM->Options.ExceptionModel != ExceptionHandling::Wasm)
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report_fatal_error(
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"-wasm-enable-eh only allowed with -exception-model=wasm");
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if (WasmEnableSjLj && TM->Options.ExceptionModel != ExceptionHandling::Wasm)
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report_fatal_error(
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"-wasm-enable-sjlj only allowed with -exception-model=wasm");
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if ((!WasmEnableEH && !WasmEnableSjLj) &&
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TM->Options.ExceptionModel == ExceptionHandling::Wasm)
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report_fatal_error(
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"-exception-model=wasm only allowed with at least one of "
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"-wasm-enable-eh or -wasm-enable-sjlj");
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// Currently it is allowed to mix Wasm EH with Emscripten SjLj as an interim
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// measure, but some code will error out at compile time in this combination.
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// See WebAssemblyLowerEmscriptenEHSjLj pass for details.
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}
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/// Create an WebAssembly architecture model.
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///
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WebAssemblyTargetMachine::WebAssemblyTargetMachine(
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const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
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: CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Large), OL),
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TLOF(new WebAssemblyTargetObjectFile()),
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UsesMultivalueABI(Options.MCOptions.getABIName() == "experimental-mv") {
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// WebAssembly type-checks instructions, but a noreturn function with a return
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// type that doesn't match the context will cause a check failure. So we lower
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// LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
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// 'unreachable' instructions which is meant for that case. Formerly, we also
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// needed to add checks to SP failure emission in the instruction selection
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// backends, but this has since been tied to TrapUnreachable and is no longer
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// necessary.
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this->Options.TrapUnreachable = true;
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this->Options.NoTrapAfterNoreturn = false;
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// WebAssembly treats each function as an independent unit. Force
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// -ffunction-sections, effectively, so that we can emit them independently.
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this->Options.FunctionSections = true;
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this->Options.DataSections = true;
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this->Options.UniqueSectionNames = true;
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basicCheckForEHAndSjLj(this);
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initAsmInfo();
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LLT::setUseExtended(true);
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// Note that we don't use setRequiresStructuredCFG(true). It disables
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// optimizations than we're ok with, and want, such as critical edge
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// splitting and tail merging.
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}
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WebAssemblyTargetMachine::~WebAssemblyTargetMachine() = default; // anchor.
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const WebAssemblySubtarget *WebAssemblyTargetMachine::getSubtargetImpl() const {
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return getSubtargetImpl(std::string(getTargetCPU()),
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std::string(getTargetFeatureString()));
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}
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const WebAssemblySubtarget *
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WebAssemblyTargetMachine::getSubtargetImpl(std::string CPU,
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std::string FS) const {
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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I = std::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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const WebAssemblySubtarget *
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WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU =
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CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
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std::string FS =
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FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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return getSubtargetImpl(CPU, FS);
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}
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namespace {
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class CoalesceFeaturesAndStripAtomics final : public ModulePass {
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// Take the union of all features used in the module and use it for each
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// function individually, since having multiple feature sets in one module
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// currently does not make sense for WebAssembly. If atomics are not enabled,
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// also strip atomic operations and thread local storage.
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static char ID;
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WebAssemblyTargetMachine *WasmTM;
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public:
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CoalesceFeaturesAndStripAtomics(WebAssemblyTargetMachine *WasmTM)
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: ModulePass(ID), WasmTM(WasmTM) {}
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bool runOnModule(Module &M) override {
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FeatureBitset Features = coalesceFeatures(M);
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std::string FeatureStr = getFeatureString(Features);
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WasmTM->setTargetFeatureString(FeatureStr);
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for (auto &F : M)
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replaceFeatures(F, FeatureStr);
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bool StrippedAtomics = false;
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bool StrippedTLS = false;
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if (!Features[WebAssembly::FeatureAtomics]) {
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StrippedAtomics = stripAtomics(M);
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StrippedTLS = stripThreadLocals(M);
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} else if (!Features[WebAssembly::FeatureBulkMemory]) {
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StrippedTLS |= stripThreadLocals(M);
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}
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if (StrippedAtomics && !StrippedTLS)
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stripThreadLocals(M);
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else if (StrippedTLS && !StrippedAtomics)
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stripAtomics(M);
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recordFeatures(M, Features, StrippedAtomics || StrippedTLS);
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// Conservatively assume we have made some change
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return true;
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}
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private:
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FeatureBitset coalesceFeatures(const Module &M) {
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// Union the features of all defined functions. Start with an empty set, so
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// that if a feature is disabled in every function, we'll compute it as
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// disabled. If any function lacks a target-features attribute, it'll
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// default to the target CPU from the `TargetMachine`.
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FeatureBitset Features;
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bool AnyDefinedFuncs = false;
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for (auto &F : M) {
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if (F.isDeclaration())
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continue;
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Features |= WasmTM->getSubtargetImpl(F)->getFeatureBits();
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AnyDefinedFuncs = true;
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}
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// If we have no defined functions, use the target CPU from the
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// `TargetMachine`.
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if (!AnyDefinedFuncs) {
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Features =
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WasmTM
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->getSubtargetImpl(std::string(WasmTM->getTargetCPU()),
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std::string(WasmTM->getTargetFeatureString()))
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->getFeatureBits();
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}
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return Features;
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}
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static std::string getFeatureString(const FeatureBitset &Features) {
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std::string Ret;
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for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
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if (Features[KV.Value])
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Ret += (StringRef("+") + KV.Key + ",").str();
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else
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Ret += (StringRef("-") + KV.Key + ",").str();
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}
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// remove trailing ','
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Ret.pop_back();
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return Ret;
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}
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void replaceFeatures(Function &F, const std::string &Features) {
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F.removeFnAttr("target-features");
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F.removeFnAttr("target-cpu");
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F.addFnAttr("target-features", Features);
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}
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bool stripAtomics(Module &M) {
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// Detect whether any atomics will be lowered, since there is no way to tell
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// whether the LowerAtomic pass lowers e.g. stores.
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bool Stripped = false;
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for (auto &F : M) {
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for (auto &B : F) {
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for (auto &I : B) {
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if (I.isAtomic()) {
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Stripped = true;
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goto done;
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}
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}
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}
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}
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done:
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if (!Stripped)
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return false;
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LowerAtomicPass Lowerer;
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FunctionAnalysisManager FAM;
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for (auto &F : M)
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Lowerer.run(F, FAM);
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return true;
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}
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bool stripThreadLocals(Module &M) {
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bool Stripped = false;
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for (auto &GV : M.globals()) {
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if (GV.isThreadLocal()) {
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// replace `@llvm.threadlocal.address.pX(GV)` with `GV`.
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for (Use &U : make_early_inc_range(GV.uses())) {
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if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(U.getUser())) {
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if (II->getIntrinsicID() == Intrinsic::threadlocal_address &&
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II->getArgOperand(0) == &GV) {
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II->replaceAllUsesWith(&GV);
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II->eraseFromParent();
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}
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}
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}
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Stripped = true;
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GV.setThreadLocal(false);
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}
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}
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return Stripped;
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}
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void recordFeatures(Module &M, const FeatureBitset &Features, bool Stripped) {
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for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
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if (Features[KV.Value]) {
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// Mark features as used
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std::string MDKey = (StringRef("wasm-feature-") + KV.Key).str();
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M.addModuleFlag(Module::ModFlagBehavior::Error, MDKey,
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wasm::WASM_FEATURE_PREFIX_USED);
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}
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}
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// Code compiled without atomics or bulk-memory may have had its atomics or
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// thread-local data lowered to nonatomic operations or non-thread-local
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// data. In that case, we mark the pseudo-feature "shared-mem" as disallowed
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// to tell the linker that it would be unsafe to allow this code ot be used
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// in a module with shared memory.
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if (Stripped) {
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M.addModuleFlag(Module::ModFlagBehavior::Error, "wasm-feature-shared-mem",
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wasm::WASM_FEATURE_PREFIX_DISALLOWED);
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}
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}
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};
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char CoalesceFeaturesAndStripAtomics::ID = 0;
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/// WebAssembly Code Generator Pass Configuration Options.
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class WebAssemblyPassConfig final : public TargetPassConfig {
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public:
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WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
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return getTM<WebAssemblyTargetMachine>();
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}
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FunctionPass *createTargetRegisterAllocator(bool) override;
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void addIRPasses() override;
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void addISelPrepare() override;
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bool addInstSelector() override;
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void addOptimizedRegAlloc() override;
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void addPostRegAlloc() override;
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bool addGCPasses() override { return false; }
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void addPreEmitPass() override;
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bool addPreISel() override;
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// No reg alloc
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bool addRegAssignAndRewriteFast() override { return false; }
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// No reg alloc
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bool addRegAssignAndRewriteOptimized() override { return false; }
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bool addIRTranslator() override;
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void addPreLegalizeMachineIR() override;
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bool addLegalizeMachineIR() override;
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void addPreRegBankSelect() override;
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bool addRegBankSelect() override;
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bool addGlobalInstructionSelect() override;
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};
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} // end anonymous namespace
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MachineFunctionInfo *WebAssemblyTargetMachine::createMachineFunctionInfo(
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BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const {
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return WebAssemblyFunctionInfo::create<WebAssemblyFunctionInfo>(Allocator, F,
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|
STI);
|
|
}
|
|
|
|
TargetTransformInfo
|
|
WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) const {
|
|
return TargetTransformInfo(std::make_unique<WebAssemblyTTIImpl>(this, F));
|
|
}
|
|
|
|
TargetPassConfig *
|
|
WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
return new WebAssemblyPassConfig(*this, PM);
|
|
}
|
|
|
|
FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
|
|
return nullptr; // No reg alloc
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// The following functions are called from lib/CodeGen/Passes.cpp to modify
|
|
// the CodeGen pass sequence.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
void WebAssemblyPassConfig::addIRPasses() {
|
|
// Add signatures to prototype-less function declarations
|
|
addPass(createWebAssemblyAddMissingPrototypes());
|
|
|
|
// Lower .llvm.global_dtors into .llvm.global_ctors with __cxa_atexit calls.
|
|
addPass(createLowerGlobalDtorsLegacyPass());
|
|
|
|
// Fix function bitcasts, as WebAssembly requires caller and callee signatures
|
|
// to match.
|
|
addPass(createWebAssemblyFixFunctionBitcasts());
|
|
|
|
// Optimize "returned" function attributes.
|
|
if (getOptLevel() != CodeGenOptLevel::None)
|
|
addPass(createWebAssemblyOptimizeReturned());
|
|
|
|
// If exception handling is not enabled and setjmp/longjmp handling is
|
|
// enabled, we lower invokes into calls and delete unreachable landingpad
|
|
// blocks. Lowering invokes when there is no EH support is done in
|
|
// TargetPassConfig::addPassesToHandleExceptions, but that runs after these IR
|
|
// passes and Emscripten SjLj handling expects all invokes to be lowered
|
|
// before.
|
|
if (!WasmEnableEmEH && !WasmEnableEH) {
|
|
addPass(createLowerInvokePass());
|
|
// The lower invoke pass may create unreachable code. Remove it in order not
|
|
// to process dead blocks in setjmp/longjmp handling.
|
|
addPass(createUnreachableBlockEliminationPass());
|
|
}
|
|
|
|
// Handle exceptions and setjmp/longjmp if enabled. Unlike Wasm EH preparation
|
|
// done in WasmEHPrepare pass, Wasm SjLj preparation shares libraries and
|
|
// transformation algorithms with Emscripten SjLj, so we run
|
|
// LowerEmscriptenEHSjLj pass also when Wasm SjLj is enabled.
|
|
if (WasmEnableEmEH || WasmEnableEmSjLj || WasmEnableSjLj)
|
|
addPass(createWebAssemblyLowerEmscriptenEHSjLj());
|
|
|
|
// Expand indirectbr instructions to switches.
|
|
addPass(createIndirectBrExpandPass());
|
|
|
|
// Try to expand `vecreduce_{and, or}` into `{any, all}_true`.
|
|
addPass(createWebAssemblyReduceToAnyAllTrue(getWebAssemblyTargetMachine()));
|
|
|
|
TargetPassConfig::addIRPasses();
|
|
}
|
|
|
|
void WebAssemblyPassConfig::addISelPrepare() {
|
|
// We need to move reference type allocas to WASM_ADDRESS_SPACE_VAR so that
|
|
// loads and stores are promoted to local.gets/local.sets.
|
|
addPass(createWebAssemblyRefTypeMem2Local());
|
|
// Lower atomics and TLS if necessary
|
|
addPass(new CoalesceFeaturesAndStripAtomics(&getWebAssemblyTargetMachine()));
|
|
|
|
// This is a no-op if atomics are not used in the module
|
|
addPass(createAtomicExpandLegacyPass());
|
|
|
|
TargetPassConfig::addISelPrepare();
|
|
}
|
|
|
|
bool WebAssemblyPassConfig::addInstSelector() {
|
|
(void)TargetPassConfig::addInstSelector();
|
|
addPass(
|
|
createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
|
|
// Run the argument-move pass immediately after the ScheduleDAG scheduler
|
|
// so that we can fix up the ARGUMENT instructions before anything else
|
|
// sees them in the wrong place.
|
|
addPass(createWebAssemblyArgumentMove());
|
|
// Set the p2align operands. This information is present during ISel, however
|
|
// it's inconvenient to collect. Collect it now, and update the immediate
|
|
// operands.
|
|
addPass(createWebAssemblySetP2AlignOperands());
|
|
|
|
// Eliminate range checks and add default targets to br_table instructions.
|
|
addPass(createWebAssemblyFixBrTableDefaults());
|
|
|
|
// unreachable is terminator, non-terminator instruction after it is not
|
|
// allowed.
|
|
addPass(createWebAssemblyCleanCodeAfterTrap());
|
|
|
|
return false;
|
|
}
|
|
|
|
void WebAssemblyPassConfig::addOptimizedRegAlloc() {
|
|
// Currently RegisterCoalesce degrades wasm debug info quality by a
|
|
// significant margin. As a quick fix, disable this for -O1, which is often
|
|
// used for debugging large applications. Disabling this increases code size
|
|
// of Emscripten core benchmarks by ~5%, which is acceptable for -O1, which is
|
|
// usually not used for production builds.
|
|
// TODO Investigate why RegisterCoalesce degrades debug info quality and fix
|
|
// it properly
|
|
if (getOptLevel() == CodeGenOptLevel::Less)
|
|
disablePass(&RegisterCoalescerID);
|
|
TargetPassConfig::addOptimizedRegAlloc();
|
|
}
|
|
|
|
void WebAssemblyPassConfig::addPostRegAlloc() {
|
|
// TODO: The following CodeGen passes don't currently support code containing
|
|
// virtual registers. Consider removing their restrictions and re-enabling
|
|
// them.
|
|
|
|
// These functions all require the NoVRegs property.
|
|
disablePass(&MachineLateInstrsCleanupID);
|
|
disablePass(&MachineCopyPropagationID);
|
|
disablePass(&PostRAMachineSinkingID);
|
|
disablePass(&PostRASchedulerID);
|
|
disablePass(&FuncletLayoutID);
|
|
disablePass(&StackMapLivenessID);
|
|
disablePass(&PatchableFunctionID);
|
|
disablePass(&ShrinkWrapID);
|
|
disablePass(&RemoveLoadsIntoFakeUsesID);
|
|
|
|
// This pass hurts code size for wasm because it can generate irreducible
|
|
// control flow.
|
|
disablePass(&MachineBlockPlacementID);
|
|
|
|
TargetPassConfig::addPostRegAlloc();
|
|
}
|
|
|
|
void WebAssemblyPassConfig::addPreEmitPass() {
|
|
TargetPassConfig::addPreEmitPass();
|
|
|
|
// Nullify DBG_VALUE_LISTs that we cannot handle.
|
|
addPass(createWebAssemblyNullifyDebugValueLists());
|
|
|
|
// Remove any unreachable blocks that may be left floating around.
|
|
// Rare, but possible. Needed for WebAssemblyFixIrreducibleControlFlow.
|
|
addPass(&UnreachableMachineBlockElimID);
|
|
|
|
// Eliminate multiple-entry loops.
|
|
addPass(createWebAssemblyFixIrreducibleControlFlow());
|
|
|
|
// Do various transformations for exception handling.
|
|
// Every CFG-changing optimizations should come before this.
|
|
if (TM->Options.ExceptionModel == ExceptionHandling::Wasm)
|
|
addPass(createWebAssemblyLateEHPrepare());
|
|
|
|
// Now that we have a prologue and epilogue and all frame indices are
|
|
// rewritten, eliminate SP and FP. This allows them to be stackified,
|
|
// colored, and numbered with the rest of the registers.
|
|
addPass(createWebAssemblyReplacePhysRegs());
|
|
|
|
// Preparations and optimizations related to register stackification.
|
|
if (getOptLevel() != CodeGenOptLevel::None) {
|
|
// Depend on LiveIntervals and perform some optimizations on it.
|
|
addPass(createWebAssemblyOptimizeLiveIntervals());
|
|
|
|
// Prepare memory intrinsic calls for register stackifying.
|
|
addPass(createWebAssemblyMemIntrinsicResults());
|
|
}
|
|
|
|
// Mark registers as representing wasm's value stack. This is a key
|
|
// code-compression technique in WebAssembly. We run this pass (and
|
|
// MemIntrinsicResults above) very late, so that it sees as much code as
|
|
// possible, including code emitted by PEI and expanded by late tail
|
|
// duplication.
|
|
addPass(createWebAssemblyRegStackify(getOptLevel()));
|
|
|
|
if (getOptLevel() != CodeGenOptLevel::None) {
|
|
// Run the register coloring pass to reduce the total number of registers.
|
|
// This runs after stackification so that it doesn't consider registers
|
|
// that become stackified.
|
|
addPass(createWebAssemblyRegColoring());
|
|
}
|
|
|
|
// Sort the blocks of the CFG into topological order, a prerequisite for
|
|
// BLOCK and LOOP markers.
|
|
addPass(createWebAssemblyCFGSort());
|
|
|
|
// Insert BLOCK and LOOP markers.
|
|
addPass(createWebAssemblyCFGStackify());
|
|
|
|
// Insert explicit local.get and local.set operators.
|
|
if (!WasmDisableExplicitLocals)
|
|
addPass(createWebAssemblyExplicitLocals());
|
|
|
|
// Lower br_unless into br_if.
|
|
addPass(createWebAssemblyLowerBrUnless());
|
|
|
|
// Perform the very last peephole optimizations on the code.
|
|
if (getOptLevel() != CodeGenOptLevel::None)
|
|
addPass(createWebAssemblyPeephole());
|
|
|
|
// Create a mapping from LLVM CodeGen virtual registers to wasm registers.
|
|
addPass(createWebAssemblyRegNumbering());
|
|
|
|
// Fix debug_values whose defs have been stackified.
|
|
if (!WasmDisableExplicitLocals)
|
|
addPass(createWebAssemblyDebugFixup());
|
|
|
|
// Collect information to prepare for MC lowering / asm printing.
|
|
addPass(createWebAssemblyMCLowerPrePass());
|
|
}
|
|
|
|
bool WebAssemblyPassConfig::addPreISel() {
|
|
TargetPassConfig::addPreISel();
|
|
addPass(createWebAssemblyLowerRefTypesIntPtrConv());
|
|
return false;
|
|
}
|
|
|
|
bool WebAssemblyPassConfig::addIRTranslator() {
|
|
addPass(new IRTranslator());
|
|
return false;
|
|
}
|
|
|
|
void WebAssemblyPassConfig::addPreLegalizeMachineIR() {
|
|
if (getOptLevel() != CodeGenOptLevel::None) {
|
|
addPass(createWebAssemblyPreLegalizerCombiner());
|
|
}
|
|
}
|
|
bool WebAssemblyPassConfig::addLegalizeMachineIR() {
|
|
addPass(new Legalizer());
|
|
return false;
|
|
}
|
|
|
|
void WebAssemblyPassConfig::addPreRegBankSelect() {
|
|
if (getOptLevel() != CodeGenOptLevel::None) {
|
|
addPass(createWebAssemblyPostLegalizerCombiner());
|
|
}
|
|
}
|
|
|
|
bool WebAssemblyPassConfig::addRegBankSelect() {
|
|
addPass(new RegBankSelect());
|
|
return false;
|
|
}
|
|
|
|
bool WebAssemblyPassConfig::addGlobalInstructionSelect() {
|
|
addPass(new InstructionSelect(getOptLevel()));
|
|
|
|
// We insert only if ISelDAG won't insert these at a later point.
|
|
if (isGlobalISelAbortEnabled()) {
|
|
addPass(createWebAssemblyArgumentMove());
|
|
addPass(createWebAssemblySetP2AlignOperands());
|
|
addPass(createWebAssemblyFixBrTableDefaults());
|
|
addPass(createWebAssemblyCleanCodeAfterTrap());
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
yaml::MachineFunctionInfo *
|
|
WebAssemblyTargetMachine::createDefaultFuncInfoYAML() const {
|
|
return new yaml::WebAssemblyFunctionInfo();
|
|
}
|
|
|
|
yaml::MachineFunctionInfo *WebAssemblyTargetMachine::convertFuncInfoToYAML(
|
|
const MachineFunction &MF) const {
|
|
const auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
|
|
return new yaml::WebAssemblyFunctionInfo(MF, *MFI);
|
|
}
|
|
|
|
bool WebAssemblyTargetMachine::parseMachineFunctionInfo(
|
|
const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
|
|
SMDiagnostic &Error, SMRange &SourceRange) const {
|
|
const auto &YamlMFI = static_cast<const yaml::WebAssemblyFunctionInfo &>(MFI);
|
|
MachineFunction &MF = PFS.MF;
|
|
MF.getInfo<WebAssemblyFunctionInfo>()->initializeBaseYamlFields(MF, YamlMFI);
|
|
return false;
|
|
}
|