11ab23c33d
Both conceptually belong to the same subtarget, so it should not be necessary to pass in the context TargetRegisterInfo to any TargetInstrInfo member. Add this reference so those superfluous arguments can be removed. Most targets placed their TargetRegisterInfo as a member in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo, so unify all targets to look the same.
145 lines
4.5 KiB
C++
145 lines
4.5 KiB
C++
//===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMTargetMachine.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/MCInst.h"
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using namespace llvm;
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI, RI) {}
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/// Return the noop instruction to use for a noop.
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MCInst ARMInstrInfo::getNop() const {
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MCInst NopInst;
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if (hasNOP()) {
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NopInst.setOpcode(ARM::HINT);
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NopInst.addOperand(MCOperand::createImm(0));
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NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::createReg(0));
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} else {
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NopInst.setOpcode(ARM::MOVr);
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NopInst.addOperand(MCOperand::createReg(ARM::R0));
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NopInst.addOperand(MCOperand::createReg(ARM::R0));
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NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::createReg(0));
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NopInst.addOperand(MCOperand::createReg(0));
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}
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return NopInst;
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}
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unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
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switch (Opc) {
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default:
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break;
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case ARM::LDR_PRE_IMM:
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case ARM::LDR_PRE_REG:
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case ARM::LDR_POST_IMM:
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case ARM::LDR_POST_REG:
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return ARM::LDRi12;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE_IMM:
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case ARM::LDRB_PRE_REG:
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case ARM::LDRB_POST_IMM:
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case ARM::LDRB_POST_REG:
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return ARM::LDRBi12;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE_IMM:
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case ARM::STR_PRE_REG:
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case ARM::STR_POST_IMM:
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case ARM::STR_POST_REG:
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return ARM::STRi12;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE_IMM:
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case ARM::STRB_PRE_REG:
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case ARM::STRB_POST_IMM:
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case ARM::STRB_POST_REG:
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return ARM::STRBi12;
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}
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return 0;
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}
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void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI) const {
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MachineFunction &MF = *MI->getParent()->getParent();
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const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
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const TargetMachine &TM = MF.getTarget();
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Module &M = *MF.getFunction().getParent();
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if (M.getStackProtectorGuard() == "tls") {
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expandLoadStackGuardBase(MI, ARM::MRC, ARM::LDRi12);
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return;
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}
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const GlobalValue *GV =
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cast<GlobalValue>((*MI->memoperands_begin())->getValue());
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bool ForceELFGOTPIC = Subtarget.isTargetELF() && !GV->isDSOLocal();
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if (!Subtarget.useMovt() || ForceELFGOTPIC) {
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// For ELF non-PIC, use GOT PIC code sequence as well because R_ARM_GOT_ABS
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// does not have assembler support.
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if (TM.isPositionIndependent() || ForceELFGOTPIC)
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expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
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else
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expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
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return;
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}
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if (!TM.isPositionIndependent()) {
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expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12);
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return;
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}
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if (!Subtarget.isGVIndirectSymbol(GV)) {
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expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12);
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return;
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}
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MachineBasicBlock &MBB = *MI->getParent();
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DebugLoc DL = MI->getDebugLoc();
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Register Reg = MI->getOperand(0).getReg();
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MachineInstrBuilder MIB;
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MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
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.addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
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auto Flags = MachineMemOperand::MOLoad |
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MachineMemOperand::MODereferenceable |
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MachineMemOperand::MOInvariant;
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MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
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MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, Align(4));
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MIB.addMemOperand(MMO);
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BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
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.addReg(Reg, RegState::Kill)
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.addImm(0)
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.cloneMemRefs(*MI)
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.add(predOps(ARMCC::AL));
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}
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