829afc4c91
Introduce two new subtarget features: - WMMA256bInsts for GFX11 WMMA instructions and - WMMA128bInsts for GFX1170 and GFX12 WMMA and SWMMAC instructions Some WMMA instructions have changed from GFX 11.0 to GFX 11.7 so new Real versions were added with "_gfx1170" suffix. For consistency all WMMA and SWMMAC GFX11.7 instructions use this suffix. To resolve decoding issues between different formats for some WMMA instructions between GFX 11 and GFX 11.7, new decoding tables were added.
230 lines
8.6 KiB
C++
230 lines
8.6 KiB
C++
//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains declaration for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#include "SIDefines.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/DataExtractor.h"
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#include <memory>
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namespace llvm {
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class MCAsmInfo;
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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class Twine;
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//===----------------------------------------------------------------------===//
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// AMDGPUDisassembler
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//===----------------------------------------------------------------------===//
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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std::unique_ptr<MCInstrInfo const> const MCII;
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const MCRegisterInfo &MRI;
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const MCAsmInfo &MAI;
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const unsigned HwModeRegClass;
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const unsigned TargetMaxInstBytes;
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mutable ArrayRef<uint8_t> Bytes;
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mutable uint64_t Literal;
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mutable bool HasLiteral;
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mutable std::optional<bool> EnableWavefrontSize32;
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unsigned CodeObjectVersion;
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const MCExpr *UCVersionW64Expr;
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const MCExpr *UCVersionW32Expr;
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const MCExpr *UCVersionMDPExpr;
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const MCExpr *createConstantSymbolExpr(StringRef Id, int64_t Val);
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void decodeImmOperands(MCInst &MI, const MCInstrInfo &MCII) const;
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII);
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~AMDGPUDisassembler() override = default;
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void setABIVersion(unsigned Version) override;
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CS) const override;
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const char* getRegClassName(unsigned RegClassID) const;
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MCOperand createRegOperand(MCRegister Reg) const;
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MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
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MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
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MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
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template <typename InsnType>
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DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
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uint64_t Address, raw_ostream &Comments) const;
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template <typename InsnType>
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DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
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MCInst &MI, InsnType Inst, uint64_t Address,
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raw_ostream &Comments) const;
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Expected<bool> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address) const override;
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Expected<bool> decodeKernelDescriptor(StringRef KdName,
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ArrayRef<uint8_t> Bytes,
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uint64_t KdAddress) const;
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Expected<bool>
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decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor,
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ArrayRef<uint8_t> Bytes,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC1.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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Expected<bool> decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC2.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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Expected<bool> decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC3.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC3.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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Expected<bool> decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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void convertEXPInst(MCInst &MI) const;
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void convertVINTERPInst(MCInst &MI) const;
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void convertFMAanyK(MCInst &MI) const;
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void convertSDWAInst(MCInst &MI) const;
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void convertMAIInst(MCInst &MI) const;
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void convertWMMAInst(MCInst &MI) const;
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void convertDPP8Inst(MCInst &MI) const;
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void convertMIMGInst(MCInst &MI) const;
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void convertVOP3DPPInst(MCInst &MI) const;
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void convertVOP3PDPPInst(MCInst &MI) const;
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void convertVOPCDPPInst(MCInst &MI) const;
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void convertVOPC64DPPInst(MCInst &MI) const;
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void convertMacDPPInst(MCInst &MI) const;
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void convertTrue16OpSel(MCInst &MI) const;
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unsigned getVgprClassId(unsigned Width) const;
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unsigned getAgprClassId(unsigned Width) const;
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unsigned getSgprClassId(unsigned Width) const;
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unsigned getTtmpClassId(unsigned Width) const;
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static MCOperand decodeIntImmed(unsigned Imm);
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MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
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MCOperand decodeMandatoryLiteral64Constant(uint64_t Imm) const;
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MCOperand decodeLiteralConstant(const MCInstrDesc &Desc,
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const MCOperandInfo &OpDesc) const;
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MCOperand decodeLiteral64Constant() const;
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MCOperand decodeSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const;
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MCOperand decodeNonVGPRSrcOp(const MCInst &Inst, unsigned Width,
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unsigned Val) const;
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MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
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MCOperand decodeSpecialReg32(unsigned Val) const;
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MCOperand decodeSpecialReg64(unsigned Val) const;
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MCOperand decodeSpecialReg96Plus(unsigned Val) const;
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MCOperand decodeSDWASrc(unsigned Width, unsigned Val) const;
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MCOperand decodeSDWASrc16(unsigned Val) const;
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MCOperand decodeSDWASrc32(unsigned Val) const;
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MCOperand decodeSDWAVopcDst(unsigned Val) const;
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MCOperand decodeBoolReg(const MCInst &Inst, unsigned Val) const;
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MCOperand decodeSplitBarrier(const MCInst &Inst, unsigned Val) const;
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MCOperand decodeDpp8FI(unsigned Val) const;
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MCOperand decodeVersionImm(unsigned Imm) const;
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int getTTmpIdx(unsigned Val) const;
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const MCInstrInfo *getMCII() const { return MCII.get(); }
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bool isVI() const;
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bool isGFX9() const;
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bool isGFX90A() const;
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bool isGFX9Plus() const;
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bool isGFX10() const;
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bool isGFX10Plus() const;
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bool isGFX11() const;
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bool isGFX1170() const;
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bool isGFX11Plus() const;
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bool isGFX12() const;
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bool isGFX12Plus() const;
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bool isGFX1250() const;
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bool isGFX1250Plus() const;
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bool isGFX13() const;
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bool isGFX13Plus() const;
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bool hasArchitectedFlatScratch() const;
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bool hasKernargPreload() const;
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bool isMacDPP(MCInst &MI) const;
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/// Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
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bool isBufferInstruction(const MCInst &MI) const;
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};
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//===----------------------------------------------------------------------===//
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// AMDGPUSymbolizer
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//===----------------------------------------------------------------------===//
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class AMDGPUSymbolizer : public MCSymbolizer {
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private:
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void *DisInfo;
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std::vector<uint64_t> ReferencedAddresses;
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public:
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AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
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void *disInfo)
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: MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
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bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
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int64_t Value, uint64_t Address, bool IsBranch,
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uint64_t Offset, uint64_t OpSize,
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uint64_t InstSize) override;
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void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
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int64_t Value,
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uint64_t Address) override;
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ArrayRef<uint64_t> getReferencedAddresses() const override {
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return ReferencedAddresses;
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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