7feb816ed0
This enables NewPM ports since it removes multiple pass dependencies on `TargetPassConfig` which we don't want to port to the NewPM. It looks like no derived classes of Combiner actually use this pointer, and it is also unused in the Combiner class.
520 lines
18 KiB
C++
520 lines
18 KiB
C++
//=== lib/CodeGen/GlobalISel/AMDGPUPostLegalizerCombiner.cpp --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// after the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUCombinerHelper.h"
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#include "AMDGPULegalizerInfo.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
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#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
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#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/Target/TargetMachine.h"
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#define GET_GICOMBINER_DEPS
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#include "AMDGPUGenPreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_DEPS
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#define DEBUG_TYPE "amdgpu-postlegalizer-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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namespace {
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#define GET_GICOMBINER_TYPES
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#include "AMDGPUGenPostLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_TYPES
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class AMDGPUPostLegalizerCombinerImpl : public Combiner {
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protected:
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const AMDGPUPostLegalizerCombinerImplRuleConfig &RuleConfig;
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const GCNSubtarget &STI;
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const SIInstrInfo &TII;
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// TODO: Make CombinerHelper methods const.
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mutable AMDGPUCombinerHelper Helper;
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public:
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AMDGPUPostLegalizerCombinerImpl(
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MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
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GISelCSEInfo *CSEInfo,
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const AMDGPUPostLegalizerCombinerImplRuleConfig &RuleConfig,
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const GCNSubtarget &STI, MachineDominatorTree *MDT,
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const LegalizerInfo *LI);
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static const char *getName() { return "AMDGPUPostLegalizerCombinerImpl"; }
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bool tryCombineAllImpl(MachineInstr &I) const;
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bool tryCombineAll(MachineInstr &I) const override;
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struct FMinFMaxLegacyInfo {
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Register LHS;
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Register RHS;
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CmpInst::Predicate Pred;
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};
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// TODO: Make sure fmin_legacy/fmax_legacy don't canonicalize
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bool matchFMinFMaxLegacy(MachineInstr &MI, MachineInstr &FCmp,
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FMinFMaxLegacyInfo &Info) const;
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void applySelectFCmpToFMinFMaxLegacy(MachineInstr &MI,
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const FMinFMaxLegacyInfo &Info) const;
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bool matchUCharToFloat(MachineInstr &MI) const;
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void applyUCharToFloat(MachineInstr &MI) const;
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bool
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matchRcpSqrtToRsq(MachineInstr &MI,
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std::function<void(MachineIRBuilder &)> &MatchInfo) const;
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bool matchFDivSqrtToRsqF16(MachineInstr &MI) const;
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void applyFDivSqrtToRsqF16(MachineInstr &MI, const Register &X) const;
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// FIXME: Should be able to have 2 separate matchdatas rather than custom
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// struct boilerplate.
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struct CvtF32UByteMatchInfo {
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Register CvtVal;
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unsigned ShiftOffset;
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};
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bool matchCvtF32UByteN(MachineInstr &MI,
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CvtF32UByteMatchInfo &MatchInfo) const;
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void applyCvtF32UByteN(MachineInstr &MI,
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const CvtF32UByteMatchInfo &MatchInfo) const;
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bool matchRemoveFcanonicalize(MachineInstr &MI, Register &Reg) const;
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// Combine unsigned buffer load and signed extension instructions to generate
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// signed buffer load instructions.
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bool matchCombineSignExtendInReg(
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MachineInstr &MI, std::pair<MachineInstr *, unsigned> &MatchInfo) const;
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void applyCombineSignExtendInReg(
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MachineInstr &MI, std::pair<MachineInstr *, unsigned> &MatchInfo) const;
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// Find the s_mul_u64 instructions where the higher bits are either
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// zero-extended or sign-extended.
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// Replace the s_mul_u64 instructions with S_MUL_I64_I32_PSEUDO if the higher
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// 33 bits are sign extended and with S_MUL_U64_U32_PSEUDO if the higher 32
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// bits are zero extended.
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bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
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private:
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#define GET_GICOMBINER_CLASS_MEMBERS
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenPostLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_CLASS_MEMBERS
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#undef AMDGPUSubtarget
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};
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#define GET_GICOMBINER_IMPL
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenPostLegalizeGICombiner.inc"
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#undef AMDGPUSubtarget
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#undef GET_GICOMBINER_IMPL
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AMDGPUPostLegalizerCombinerImpl::AMDGPUPostLegalizerCombinerImpl(
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MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
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GISelCSEInfo *CSEInfo,
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const AMDGPUPostLegalizerCombinerImplRuleConfig &RuleConfig,
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const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI)
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: Combiner(MF, CInfo, &VT, CSEInfo), RuleConfig(RuleConfig), STI(STI),
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TII(*STI.getInstrInfo()),
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Helper(Observer, B, /*IsPreLegalize*/ false, &VT, MDT, LI, STI),
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#define GET_GICOMBINER_CONSTRUCTOR_INITS
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#include "AMDGPUGenPostLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_CONSTRUCTOR_INITS
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{
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}
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bool AMDGPUPostLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
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if (tryCombineAllImpl(MI))
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return true;
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switch (MI.getOpcode()) {
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case TargetOpcode::G_SHL:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_ASHR:
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// On some subtargets, 64-bit shift is a quarter rate instruction. In the
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// common case, splitting this into a move and a 32-bit shift is faster and
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// the same code size.
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return Helper.tryCombineShiftToUnmerge(MI, 32);
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}
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return false;
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchFMinFMaxLegacy(
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MachineInstr &MI, MachineInstr &FCmp, FMinFMaxLegacyInfo &Info) const {
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if (!MRI.hasOneNonDBGUse(FCmp.getOperand(0).getReg()))
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return false;
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Info.Pred =
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static_cast<CmpInst::Predicate>(FCmp.getOperand(1).getPredicate());
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Info.LHS = FCmp.getOperand(2).getReg();
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Info.RHS = FCmp.getOperand(3).getReg();
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Register True = MI.getOperand(2).getReg();
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Register False = MI.getOperand(3).getReg();
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// TODO: Handle case where the the selected value is an fneg and the compared
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// constant is the negation of the selected value.
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if ((Info.LHS != True || Info.RHS != False) &&
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(Info.LHS != False || Info.RHS != True))
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return false;
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// Invert the predicate if necessary so that the apply function can assume
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// that the select operands are the same as the fcmp operands.
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// (select (fcmp P, L, R), R, L) -> (select (fcmp !P, L, R), L, R)
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if (Info.LHS != True)
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Info.Pred = CmpInst::getInversePredicate(Info.Pred);
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// Only match </<=/>=/> not ==/!= etc.
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return Info.Pred != CmpInst::getSwappedPredicate(Info.Pred);
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}
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void AMDGPUPostLegalizerCombinerImpl::applySelectFCmpToFMinFMaxLegacy(
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MachineInstr &MI, const FMinFMaxLegacyInfo &Info) const {
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unsigned Opc = (Info.Pred & CmpInst::FCMP_OGT) ? AMDGPU::G_AMDGPU_FMAX_LEGACY
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: AMDGPU::G_AMDGPU_FMIN_LEGACY;
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Register X = Info.LHS;
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Register Y = Info.RHS;
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if (Info.Pred == CmpInst::getUnorderedPredicate(Info.Pred)) {
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// We need to permute the operands to get the correct NaN behavior. The
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// selected operand is the second one based on the failing compare with NaN,
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// so permute it based on the compare type the hardware uses.
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std::swap(X, Y);
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}
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B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags());
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MI.eraseFromParent();
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchUCharToFloat(
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MachineInstr &MI) const {
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Register DstReg = MI.getOperand(0).getReg();
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// TODO: We could try to match extracting the higher bytes, which would be
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// easier if i8 vectors weren't promoted to i32 vectors, particularly after
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// types are legalized. v4i8 -> v4f32 is probably the only case to worry
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// about in practice.
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LLT Ty = MRI.getType(DstReg);
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if (Ty == LLT::scalar(32) || Ty == LLT::scalar(16)) {
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Register SrcReg = MI.getOperand(1).getReg();
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unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
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assert(SrcSize == 16 || SrcSize == 32 || SrcSize == 64);
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const APInt Mask = APInt::getHighBitsSet(SrcSize, SrcSize - 8);
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return Helper.getValueTracking()->maskedValueIsZero(SrcReg, Mask);
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}
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return false;
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}
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void AMDGPUPostLegalizerCombinerImpl::applyUCharToFloat(
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MachineInstr &MI) const {
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const LLT S32 = LLT::scalar(32);
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Register DstReg = MI.getOperand(0).getReg();
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Register SrcReg = MI.getOperand(1).getReg();
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LLT Ty = MRI.getType(DstReg);
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LLT SrcTy = MRI.getType(SrcReg);
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if (SrcTy != S32)
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SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0);
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if (Ty == S32) {
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B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, {SrcReg},
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MI.getFlags());
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} else {
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auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, {SrcReg},
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MI.getFlags());
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B.buildFPTrunc(DstReg, Cvt0, MI.getFlags());
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}
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MI.eraseFromParent();
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchRcpSqrtToRsq(
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MachineInstr &MI,
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std::function<void(MachineIRBuilder &)> &MatchInfo) const {
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auto getRcpSrc = [=](const MachineInstr &MI) -> MachineInstr * {
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if (!MI.getFlag(MachineInstr::FmContract))
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return nullptr;
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if (auto *GI = dyn_cast<GIntrinsic>(&MI)) {
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if (GI->is(Intrinsic::amdgcn_rcp))
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return MRI.getVRegDef(MI.getOperand(2).getReg());
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}
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return nullptr;
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};
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auto getSqrtSrc = [=](const MachineInstr &MI) -> MachineInstr * {
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if (!MI.getFlag(MachineInstr::FmContract))
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return nullptr;
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MachineInstr *SqrtSrcMI = nullptr;
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auto Match =
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mi_match(MI.getOperand(0).getReg(), MRI, m_GFSqrt(m_MInstr(SqrtSrcMI)));
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(void)Match;
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return SqrtSrcMI;
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};
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MachineInstr *RcpSrcMI = nullptr, *SqrtSrcMI = nullptr;
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// rcp(sqrt(x))
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if ((RcpSrcMI = getRcpSrc(MI)) && (SqrtSrcMI = getSqrtSrc(*RcpSrcMI))) {
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MatchInfo = [SqrtSrcMI, &MI](MachineIRBuilder &B) {
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B.buildIntrinsic(Intrinsic::amdgcn_rsq, {MI.getOperand(0)})
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.addUse(SqrtSrcMI->getOperand(0).getReg())
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.setMIFlags(MI.getFlags());
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};
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return true;
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}
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// sqrt(rcp(x))
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if ((SqrtSrcMI = getSqrtSrc(MI)) && (RcpSrcMI = getRcpSrc(*SqrtSrcMI))) {
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MatchInfo = [RcpSrcMI, &MI](MachineIRBuilder &B) {
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B.buildIntrinsic(Intrinsic::amdgcn_rsq, {MI.getOperand(0)})
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.addUse(RcpSrcMI->getOperand(0).getReg())
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.setMIFlags(MI.getFlags());
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};
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return true;
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}
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return false;
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchFDivSqrtToRsqF16(
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MachineInstr &MI) const {
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Register Sqrt = MI.getOperand(2).getReg();
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return MRI.hasOneNonDBGUse(Sqrt);
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}
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void AMDGPUPostLegalizerCombinerImpl::applyFDivSqrtToRsqF16(
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MachineInstr &MI, const Register &X) const {
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Register Dst = MI.getOperand(0).getReg();
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Register Y = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(Dst);
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uint32_t Flags = MI.getFlags();
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Register RSQ = B.buildIntrinsic(Intrinsic::amdgcn_rsq, {DstTy})
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.addUse(X)
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.setMIFlags(Flags)
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.getReg(0);
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B.buildFMul(Dst, RSQ, Y, Flags);
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MI.eraseFromParent();
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchCvtF32UByteN(
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MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo) const {
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Register SrcReg = MI.getOperand(1).getReg();
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// Look through G_ZEXT.
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bool IsShr = mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg)));
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Register Src0;
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int64_t ShiftAmt;
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IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
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if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) {
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const unsigned Offset = MI.getOpcode() - AMDGPU::G_AMDGPU_CVT_F32_UBYTE0;
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unsigned ShiftOffset = 8 * Offset;
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if (IsShr)
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ShiftOffset += ShiftAmt;
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else
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ShiftOffset -= ShiftAmt;
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MatchInfo.CvtVal = Src0;
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MatchInfo.ShiftOffset = ShiftOffset;
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return ShiftOffset < 32 && ShiftOffset >= 8 && (ShiftOffset % 8) == 0;
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}
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// TODO: Simplify demanded bits.
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return false;
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}
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void AMDGPUPostLegalizerCombinerImpl::applyCvtF32UByteN(
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MachineInstr &MI, const CvtF32UByteMatchInfo &MatchInfo) const {
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unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8;
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const LLT S32 = LLT::scalar(32);
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Register CvtSrc = MatchInfo.CvtVal;
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LLT SrcTy = MRI.getType(MatchInfo.CvtVal);
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if (SrcTy != S32) {
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assert(SrcTy.isScalar() && SrcTy.getSizeInBits() >= 8);
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CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0);
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}
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assert(MI.getOpcode() != NewOpc);
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B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
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MI.eraseFromParent();
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchRemoveFcanonicalize(
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MachineInstr &MI, Register &Reg) const {
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const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
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MF.getSubtarget().getTargetLowering());
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Reg = MI.getOperand(1).getReg();
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return TLI->isCanonicalized(Reg, MF);
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}
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// The buffer_load_{i8, i16} intrinsics are initially lowered as
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// buffer_load_{u8, u16} instructions. Here, the buffer_load_{u8, u16}
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// instructions are combined with sign extension instrucions in order to
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// generate buffer_load_{i8, i16} instructions.
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// Identify buffer_load_{u8, u16}.
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bool AMDGPUPostLegalizerCombinerImpl::matchCombineSignExtendInReg(
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MachineInstr &MI, std::pair<MachineInstr *, unsigned> &MatchData) const {
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Register LoadReg = MI.getOperand(1).getReg();
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if (!MRI.hasOneNonDBGUse(LoadReg))
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return false;
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// Check if the first operand of the sign extension is a subword buffer load
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// instruction.
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MachineInstr *LoadMI = MRI.getVRegDef(LoadReg);
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int64_t Width = MI.getOperand(2).getImm();
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switch (LoadMI->getOpcode()) {
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case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE:
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MatchData = {LoadMI, AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE};
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return Width == 8;
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case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT:
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MatchData = {LoadMI, AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT};
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return Width == 16;
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case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE:
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MatchData = {LoadMI, AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE};
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return Width == 8;
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case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT:
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MatchData = {LoadMI, AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT};
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return Width == 16;
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}
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return false;
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}
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// Combine buffer_load_{u8, u16} and the sign extension instruction to generate
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// buffer_load_{i8, i16}.
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void AMDGPUPostLegalizerCombinerImpl::applyCombineSignExtendInReg(
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MachineInstr &MI, std::pair<MachineInstr *, unsigned> &MatchData) const {
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auto [LoadMI, NewOpcode] = MatchData;
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LoadMI->setDesc(TII.get(NewOpcode));
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// Update the destination register of the load with the destination register
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// of the sign extension.
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Register SignExtendInsnDst = MI.getOperand(0).getReg();
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LoadMI->getOperand(0).setReg(SignExtendInsnDst);
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// Remove the sign extension.
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MI.eraseFromParent();
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64(
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MachineInstr &MI, unsigned &NewOpcode) const {
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Register Src0 = MI.getOperand(1).getReg();
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Register Src1 = MI.getOperand(2).getReg();
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if (MRI.getType(Src0) != LLT::scalar(64))
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return false;
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if (VT->getKnownBits(Src1).countMinLeadingZeros() >= 32 &&
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VT->getKnownBits(Src0).countMinLeadingZeros() >= 32) {
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NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32;
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return true;
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}
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if (VT->computeNumSignBits(Src1) >= 33 &&
|
|
VT->computeNumSignBits(Src0) >= 33) {
|
|
NewOpcode = AMDGPU::G_AMDGPU_S_MUL_I64_I32;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// Pass boilerplate
|
|
// ================
|
|
|
|
class AMDGPUPostLegalizerCombiner : public MachineFunctionPass {
|
|
public:
|
|
static char ID;
|
|
|
|
AMDGPUPostLegalizerCombiner(bool IsOptNone = false);
|
|
|
|
StringRef getPassName() const override {
|
|
return "AMDGPUPostLegalizerCombiner";
|
|
}
|
|
|
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
|
|
|
private:
|
|
bool IsOptNone;
|
|
AMDGPUPostLegalizerCombinerImplRuleConfig RuleConfig;
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesCFG();
|
|
getSelectionDAGFallbackAnalysisUsage(AU);
|
|
AU.addRequired<GISelValueTrackingAnalysisLegacy>();
|
|
AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
|
|
if (!IsOptNone) {
|
|
AU.addRequired<MachineDominatorTreeWrapperPass>();
|
|
AU.addPreserved<MachineDominatorTreeWrapperPass>();
|
|
}
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
|
|
: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
|
|
if (!RuleConfig.parseCommandLineOption())
|
|
report_fatal_error("Invalid rule identifier");
|
|
}
|
|
|
|
bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
|
|
if (MF.getProperties().hasFailedISel())
|
|
return false;
|
|
const Function &F = MF.getFunction();
|
|
bool EnableOpt =
|
|
MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
|
|
|
|
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
|
|
const AMDGPULegalizerInfo *LI =
|
|
static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
|
|
|
|
GISelValueTracking *VT =
|
|
&getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
|
|
MachineDominatorTree *MDT =
|
|
IsOptNone ? nullptr
|
|
: &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
|
|
|
|
CombinerInfo CInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
|
|
LI, EnableOpt, F.hasOptSize(), F.hasMinSize());
|
|
// Disable fixed-point iteration to reduce compile-time
|
|
CInfo.MaxIterations = 1;
|
|
CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
|
|
// Legalizer performs DCE, so a full DCE pass is unnecessary.
|
|
CInfo.EnableFullDCE = false;
|
|
AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, *VT, /*CSEInfo*/ nullptr,
|
|
RuleConfig, ST, MDT, LI);
|
|
return Impl.combineMachineInstrs();
|
|
}
|
|
|
|
char AMDGPUPostLegalizerCombiner::ID = 0;
|
|
INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
|
|
"Combine AMDGPU machine instrs after legalization", false,
|
|
false)
|
|
INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
|
|
INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
|
|
"Combine AMDGPU machine instrs after legalization", false,
|
|
false)
|
|
|
|
FunctionPass *llvm::createAMDGPUPostLegalizeCombiner(bool IsOptNone) {
|
|
return new AMDGPUPostLegalizerCombiner(IsOptNone);
|
|
}
|