Factor out the handling of coalesced preg COPYs from SystemZMachineScheduler.cpp into MachineScheduler.cpp. This extends the handling to other types of instructions than COPYs or immediate loads, such as Load Address and takes care of maintaining the original input order if both SUs are biased the same way in the same zone. Another target that uses GenericScheduler can enable this by setting the new MachineSchedPolicy member BiasPRegsExtra to true (default false). In a derived scheduling strategy, this could be used either by passing /*BiasPRegsExtra=*/true to biasPhysReg() (extra instruction detection), or by calling tryBiasPhysRegs() instead which also preserves the original order if biased the same way.
184 KiB
184 KiB