6bc0faf67d
We are currently only emitting Vtables that have an 'immediate' need to emit. There rest, we are supposed to add to a list and emit at the end of the translation unit if necessary. This patch implements that infrastructure. The test added is from classic-codegen and came in at the same time as the deferred vtable emission over there, and only works with deferred vtable emission, and while it does test the deferred emission, tests quite a bit more than that. AND since it came in with the same functionality in classic codegen, seemed to make sense to come in here too.
155 lines
8.2 KiB
C++
155 lines
8.2 KiB
C++
// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir
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// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR
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// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
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// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll
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// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG
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// Test the record layout for a class with a primary virtual base.
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class Base {
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public:
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virtual void f();
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};
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class Derived : public virtual Base {};
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void f() {
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Derived d;
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d.f();
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}
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class DerivedFinal final : public virtual Base {};
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void g() {
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DerivedFinal df;
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df.f();
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}
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// CIR: !rec_Base = !cir.record<class "Base" {!cir.vptr}>
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// CIR: !rec_Derived = !cir.record<class "Derived" {!rec_Base}>
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// CIR: !rec_DerivedFinal = !cir.record<class "DerivedFinal" {!rec_Base}>
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// LLVM: %class.Derived = type { %class.Base }
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// LLVM: %class.Base = type { ptr }
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// LLVM: %class.DerivedFinal = type { %class.Base }
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// OGCG: %class.Derived = type { %class.Base }
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// OGCG: %class.Base = type { ptr }
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// OGCG: %class.DerivedFinal = type { %class.Base }
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// Test the constructor handling for a class with a virtual base.
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struct A {
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int a;
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};
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struct B: virtual A {
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int b;
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};
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void ppp() { B b; }
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// Note: OGCG speculatively emits the VTT and VTables. This is not yet implemented in CIR.
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// Vtable definition for B
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// CIR: cir.global "private" {{.*}}@_ZTV1B = #cir.vtable<{#cir.const_array<[#cir.ptr<12 : i64> : !cir.ptr<!u8i>, #cir.ptr<null> : !cir.ptr<!u8i>, #cir.global_view<@_ZTI1B> : !cir.ptr<!u8i>]> : !cir.array<!cir.ptr<!u8i> x 3>}> : !rec_anon_struct3 {alignment = 8 : i64}
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// LLVM: @_ZTV1B = linkonce_odr global { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 12 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8
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// OGCG: @_ZTV1B = linkonce_odr unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 12 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8
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// CIR: cir.func {{.*}}@_Z1fv()
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// CIR: %[[D:.+]] = cir.alloca !rec_Derived, !cir.ptr<!rec_Derived>, ["d", init]
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// CIR: cir.call @_ZN7DerivedC1Ev(%[[D]]) nothrow : (!cir.ptr<!rec_Derived> {{.*}}) -> ()
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// CIR: %[[VPTR_PTR:.+]] = cir.vtable.get_vptr %[[D]] : !cir.ptr<!rec_Derived> -> !cir.ptr<!cir.vptr>
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// CIR: %[[VPTR:.+]] = cir.load {{.*}} %[[VPTR_PTR]] : !cir.ptr<!cir.vptr>, !cir.vptr
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// CIR: %[[VPTR_I8:.+]] = cir.cast bitcast %[[VPTR]] : !cir.vptr -> !cir.ptr<!u8i>
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// CIR: %[[NEG32:.+]] = cir.const #cir.int<-32> : !s64i
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// CIR: %[[ADJ_VPTR_I8:.+]] = cir.ptr_stride %[[VPTR_I8]], %[[NEG32]] : (!cir.ptr<!u8i>, !s64i) -> !cir.ptr<!u8i>
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// CIR: %[[OFFSET_PTR:.+]] = cir.cast bitcast %[[ADJ_VPTR_I8]] : !cir.ptr<!u8i> -> !cir.ptr<!s64i>
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// CIR: %[[OFFSET:.+]] = cir.load {{.*}} %[[OFFSET_PTR]] : !cir.ptr<!s64i>, !s64i
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// CIR: %[[D_I8:.+]] = cir.cast bitcast %[[D]] : !cir.ptr<!rec_Derived> -> !cir.ptr<!u8i>
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// CIR: %[[ADJ_THIS_I8:.+]] = cir.ptr_stride %[[D_I8]], %[[OFFSET]] : (!cir.ptr<!u8i>, !s64i) -> !cir.ptr<!u8i>
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// CIR: %[[ADJ_THIS_D:.+]] = cir.cast bitcast %[[ADJ_THIS_I8]] : !cir.ptr<!u8i> -> !cir.ptr<!rec_Derived>
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// CIR: %[[BASE_THIS:.+]] = cir.cast bitcast %[[ADJ_THIS_D]] : !cir.ptr<!rec_Derived> -> !cir.ptr<!rec_Base>
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// CIR: %[[BASE_VPTR_PTR:.+]] = cir.vtable.get_vptr %[[BASE_THIS]] : !cir.ptr<!rec_Base> -> !cir.ptr<!cir.vptr>
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// CIR: %[[BASE_VPTR:.+]] = cir.load {{.*}} %[[BASE_VPTR_PTR]] : !cir.ptr<!cir.vptr>, !cir.vptr
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// CIR: %[[SLOT_PTR:.+]] = cir.vtable.get_virtual_fn_addr %[[BASE_VPTR]][0] : !cir.vptr -> !cir.ptr<!cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>>
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// CIR: %[[FN:.+]] = cir.load {{.*}} %[[SLOT_PTR]] : !cir.ptr<!cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>>, !cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>
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// CIR: cir.call %[[FN]](%[[BASE_THIS]]) : (!cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>, !cir.ptr<!rec_Base> {{.*}}) -> ()
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// CIR: cir.return
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// CIR: cir.func {{.*}}@_Z1gv()
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// CIR: %[[DF:.+]] = cir.alloca !rec_DerivedFinal, !cir.ptr<!rec_DerivedFinal>, ["df", init]
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// CIR: cir.call @_ZN12DerivedFinalC1Ev(%[[DF]]) nothrow : (!cir.ptr<!rec_DerivedFinal> {{.*}}) -> ()
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// CIR: %[[BASE_THIS_2:.+]] = cir.base_class_addr %[[DF]] : !cir.ptr<!rec_DerivedFinal> nonnull [0] -> !cir.ptr<!rec_Base>
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// CIR: %[[BASE_VPTR_PTR_2:.+]] = cir.vtable.get_vptr %[[BASE_THIS_2]] : !cir.ptr<!rec_Base> -> !cir.ptr<!cir.vptr>
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// CIR: %[[BASE_VPTR_2:.+]] = cir.load {{.*}} %[[BASE_VPTR_PTR_2]] : !cir.ptr<!cir.vptr>, !cir.vptr
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// CIR: %[[SLOT_PTR_2:.+]] = cir.vtable.get_virtual_fn_addr %[[BASE_VPTR_2]][0] : !cir.vptr -> !cir.ptr<!cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>>
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// CIR: %[[FN_2:.+]] = cir.load {{.*}} %[[SLOT_PTR_2]] : !cir.ptr<!cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>>, !cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>
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// CIR: cir.call %[[FN_2]](%[[BASE_THIS_2]]) : (!cir.ptr<!cir.func<(!cir.ptr<!rec_Base>)>>, !cir.ptr<!rec_Base> {{.*}}) -> ()
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// CIR: cir.return
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// LLVM: define {{.*}}void @_Z1fv(){{.*}}
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// LLVM: %[[D:.+]] = alloca {{.*}}
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// LLVM: call void @_ZN7DerivedC1Ev(ptr {{.*}} %[[D]])
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// LLVM: %[[VPTR_ADDR:.+]] = load ptr, ptr %[[D]]
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// LLVM: %[[NEG32_PTR:.+]] = getelementptr i8, ptr %[[VPTR_ADDR]], i64 -32
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// LLVM: %[[OFF:.+]] = load i64, ptr %[[NEG32_PTR]]
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// LLVM: %[[ADJ_THIS:.+]] = getelementptr i8, ptr %[[D]], i64 %[[OFF]]
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// LLVM: %[[VFN_TAB:.+]] = load ptr, ptr %[[ADJ_THIS]]
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// LLVM: %[[SLOT0:.+]] = getelementptr inbounds ptr, ptr %[[VFN_TAB]], i32 0
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// LLVM: %[[VFN:.+]] = load ptr, ptr %[[SLOT0]]
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// LLVM: call void %[[VFN]](ptr {{.*}}%[[ADJ_THIS]])
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// LLVM: ret void
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// LLVM: define {{.*}}void @_Z1gv(){{.*}}
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// LLVM: %[[DF:.+]] = alloca {{.*}}
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// LLVM: call void @_ZN12DerivedFinalC1Ev(ptr {{.*}} %[[DF]])
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// LLVM: %[[VPTR2:.+]] = load ptr, ptr %[[DF]]
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// LLVM: %[[SLOT0_2:.+]] = getelementptr inbounds ptr, ptr %[[VPTR2]], i32 0
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// LLVM: %[[VFN2:.+]] = load ptr, ptr %[[SLOT0_2]]
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// LLVM: call void %[[VFN2]](ptr {{.*}}%[[DF]])
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// LLVM: ret void
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// OGCG: define {{.*}}void @_Z1fv()
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// OGCG: %[[D:.+]] = alloca {{.*}}
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// OGCG: call void @_ZN7DerivedC1Ev(ptr {{.*}} %[[D]])
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// OGCG: %[[VTABLE:.+]] = load ptr, ptr %[[D]]
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// OGCG: %[[NEG32_PTR:.+]] = getelementptr i8, ptr %[[VTABLE]], i64 -32
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// OGCG: %[[OFF:.+]] = load i64, ptr %[[NEG32_PTR]]
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// OGCG: %[[ADJ_THIS:.+]] = getelementptr inbounds i8, ptr %[[D]], i64 %[[OFF]]
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// OGCG: call void @_ZN4Base1fEv(ptr {{.*}} %[[ADJ_THIS]])
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// OGCG: ret void
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// OGCG: define {{.*}}void @_Z1gv()
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// OGCG: %[[DF:.+]] = alloca {{.*}}
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// OGCG: call void @_ZN12DerivedFinalC1Ev(ptr {{.*}} %[[DF]])
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// OGCG: call void @_ZN4Base1fEv(ptr {{.*}} %[[DF]])
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// OGCG: ret void
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// Constructor for B
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// CIR: cir.func {{.*}} @_ZN1BC1Ev(%arg0: !cir.ptr<!rec_B>
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// CIR: %[[THIS_ADDR:.*]] = cir.alloca !cir.ptr<!rec_B>, !cir.ptr<!cir.ptr<!rec_B>>, ["this", init]
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// CIR: cir.store %arg0, %[[THIS_ADDR]] : !cir.ptr<!rec_B>, !cir.ptr<!cir.ptr<!rec_B>>
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// CIR: %[[THIS:.*]] = cir.load %[[THIS_ADDR]] : !cir.ptr<!cir.ptr<!rec_B>>, !cir.ptr<!rec_B>
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// CIR: %[[BASE_A_ADDR:.*]] = cir.base_class_addr %[[THIS]] : !cir.ptr<!rec_B> nonnull [12] -> !cir.ptr<!rec_A>
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// CIR: %[[VTABLE:.*]] = cir.vtable.address_point(@_ZTV1B, address_point = <index = 0, offset = 3>) : !cir.vptr
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// CIR: %[[B_VPTR:.*]] = cir.vtable.get_vptr %[[THIS]] : !cir.ptr<!rec_B> -> !cir.ptr<!cir.vptr>
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// CIR: cir.store align(8) %[[VTABLE]], %[[B_VPTR]] : !cir.vptr, !cir.ptr<!cir.vptr>
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// CIR: cir.return
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// LLVM: define{{.*}} void @_ZN1BC1Ev(ptr {{.*}} %[[THIS_ARG:.*]]){{.*}} {
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// LLVM: %[[THIS_ADDR:.*]] = alloca ptr
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// LLVM: store ptr %[[THIS_ARG]], ptr %[[THIS_ADDR]]
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// LLVM: %[[THIS:.*]] = load ptr, ptr %[[THIS_ADDR]]
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// LLVM: %[[BASE_A_ADDR:.*]] = getelementptr i8, ptr %[[THIS]], i32 12
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// LLVM: store ptr getelementptr inbounds nuw (i8, ptr @_ZTV1B, i64 24), ptr %[[THIS]]
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// LLVM: ret void
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// OGCG: define{{.*}} void @_ZN1BC1Ev(ptr {{.*}} %[[THIS_ARG:.*]])
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// OGCG: %[[THIS_ADDR:.*]] = alloca ptr
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// OGCG: store ptr %[[THIS_ARG]], ptr %[[THIS_ADDR]]
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// OGCG: %[[THIS:.*]] = load ptr, ptr %[[THIS_ADDR]]
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// OGCG: %[[BASE_A_ADDR:.*]] = getelementptr inbounds i8, ptr %[[THIS]], i64 12
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// OGCG: store ptr getelementptr inbounds inrange(-24, 0) ({ [3 x ptr] }, ptr @_ZTV1B, i32 0, i32 0, i32 3), ptr %[[THIS]]
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// OGCG: ret void
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