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[Clang][PowerPC] Add DMF crypto builtins for extended mnemonics (#185961)

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This commit adds new Clang builtins for the crypto extended mnemonics: 
void __builtin_dmsha256hash (__dmr1024 *, __dmr1024 *)
void __builtin_dmsha512hash (__dmr1024 *, __dmr1024 *)
void __builtin_dmsha3dw (__dmr2048 *)
void __builtin_dmcryshash (__dmr2048 *)
void __builtin_dmxxsha3512pad (__dmr1024 *, vec_t, uint1)
void __builtin_dmxxsha3384pad (__dmr1024 *, vec_t, uint1)
void __builtin_dmxxsha3256pad (__dmr1024 *, vec_t, uint1)
void __builtin_dmxxsha3224pad (__dmr1024 *, vec_t, uint1)
void __builtin_dmxxshake256pad (__dmr1024 *, vec_t, uint1)
void __builtin_dmxxshake128pad (__dmr1024 *, vec_t, uint1)
void __builtin_dmxxsha384512pad (__dmr1024 *, vec_t)
void __builtin_dmxxsha224256pad (__dmr1024 *, vec_t)
This commit is contained in:
Maryam Moghadas
2026-04-21 13:51:45 -04:00
committed by GitHub
parent 06b85c8bb2
commit d794e04651
6 changed files with 1019 additions and 71 deletions
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24
clang/include/clang/Basic/BuiltinsPPC.def
View File

@@ -1137,6 +1137,30 @@ UNALIASED_CUSTOM_BUILTIN(mma_dmsha3hash, "vW2048*Ii", true,
"mma,isa-future-instructions")
UNALIASED_CUSTOM_BUILTIN(mma_dmxxshapad, "vW1024*VIiIiIi", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmsha256hash, mma_dmsha2hash, "vW1024*W1024*", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmsha512hash, mma_dmsha2hash, "vW1024*W1024*", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmsha3dw, mma_dmsha3hash, "vW2048*", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmcryshash, mma_dmsha3hash, "vW2048*", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxsha3512pad, mma_dmxxshapad, "vW1024*Vi1", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxsha3384pad, mma_dmxxshapad, "vW1024*Vi1", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxsha3256pad, mma_dmxxshapad, "vW1024*Vi1", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxsha3224pad, mma_dmxxshapad, "vW1024*Vi1", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxshake256pad, mma_dmxxshapad, "vW1024*Vi1", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxshake128pad, mma_dmxxshapad, "vW1024*Vi1", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxsha384512pad, mma_dmxxshapad, "vW1024*V", true,
"mma,isa-future-instructions")
CUSTOM_BUILTIN(dmxxsha224256pad, mma_dmxxshapad, "vW1024*V", true,
"mma,isa-future-instructions")
// MMA builtins with positive/negative multiply/accumulate.
UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvf16ger2, "vW512*VV",

74
clang/lib/CodeGen/TargetBuiltins/PPC.cpp
View File

@@ -1160,15 +1160,79 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
Value *Acc = Builder.CreateLoad(Addr);
CallOps.push_back(Acc);
}
if (BuiltinID == PPC::BI__builtin_dmmr ||
BuiltinID == PPC::BI__builtin_dmxor ||
BuiltinID == PPC::BI__builtin_disassemble_dmr ||
BuiltinID == PPC::BI__builtin_mma_dmsha2hash) {
switch (BuiltinID) {
case PPC::BI__builtin_dmmr:
case PPC::BI__builtin_dmxor:
case PPC::BI__builtin_mma_dmsha2hash: {
Address Addr = EmitPointerWithAlignment(E->getArg(1));
Ops[1] = Builder.CreateLoad(Addr);
break;
}
if (BuiltinID == PPC::BI__builtin_disassemble_dmr)
case PPC::BI__builtin_disassemble_dmr: {
Ops[1] = Builder.CreateLoad(EmitPointerWithAlignment(E->getArg(1)));
return Builder.CreateAlignedStore(Ops[1], Ops[0], MaybeAlign());
}
case PPC::BI__builtin_dmsha256hash:
case PPC::BI__builtin_dmsha512hash: {
Ops[1] = Builder.CreateLoad(EmitPointerWithAlignment(E->getArg(1)));
int Imm = (BuiltinID == PPC::BI__builtin_dmsha256hash) ? 0 : 1;
Ops.push_back(llvm::ConstantInt::get(Int32Ty, Imm));
break;
}
case PPC::BI__builtin_dmsha3dw:
Ops.push_back(llvm::ConstantInt::get(Int32Ty, 0));
break;
case PPC::BI__builtin_dmcryshash:
Ops.push_back(llvm::ConstantInt::get(Int32Ty, 12));
break;
case PPC::BI__builtin_dmxxsha384512pad:
case PPC::BI__builtin_dmxxsha224256pad: {
int Imm = (BuiltinID == PPC::BI__builtin_dmxxsha384512pad) ? 2 : 3;
Ops.push_back(ConstantInt::get(Int32Ty, Imm));
Ops.push_back(ConstantInt::get(Int32Ty, 0));
Ops.push_back(ConstantInt::get(Int32Ty, 0));
break;
}
case PPC::BI__builtin_dmxxsha3512pad:
case PPC::BI__builtin_dmxxsha3384pad:
case PPC::BI__builtin_dmxxsha3256pad:
case PPC::BI__builtin_dmxxsha3224pad:
case PPC::BI__builtin_dmxxshake256pad:
case PPC::BI__builtin_dmxxshake128pad: {
Value *E_val = Ops[2];
int ID, BL;
switch (BuiltinID) {
case PPC::BI__builtin_dmxxsha3512pad:
ID = 0;
BL = 0;
break;
case PPC::BI__builtin_dmxxsha3384pad:
ID = 0;
BL = 1;
break;
case PPC::BI__builtin_dmxxsha3256pad:
ID = 0;
BL = 2;
break;
case PPC::BI__builtin_dmxxsha3224pad:
ID = 0;
BL = 3;
break;
case PPC::BI__builtin_dmxxshake256pad:
ID = 1;
BL = 0;
break;
case PPC::BI__builtin_dmxxshake128pad:
ID = 1;
BL = 1;
break;
}
Ops[2] = ConstantInt::get(Int32Ty, ID);
Ops.push_back(E_val);
Ops.push_back(ConstantInt::get(Int32Ty, BL));
break;
}
}
for (unsigned i=1; i<Ops.size(); i++)
CallOps.push_back(Ops[i]);
llvm::Function *F = CGM.getIntrinsic(ID);

402
clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
View File

@@ -8,17 +8,17 @@
// CHECK-LABEL: define dso_local void @test_dmxvi8gerx4(
// CHECK-SAME: ptr noundef readnone captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6:![0-9]+]]
// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC]])
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8:![0-9]+]]
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7:![0-9]+]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxvi8gerx4(
// AIX-SAME: ptr noundef readnone captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6:![0-9]+]]
// AIX-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5:![0-9]+]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC]])
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8:![0-9]+]]
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7:![0-9]+]]
// AIX-NEXT: ret void
//
void test_dmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -31,17 +31,17 @@ void test_dmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector unsigned
// CHECK-LABEL: define dso_local void @test_pmdmxvi8gerx4(
// CHECK-SAME: ptr noundef readnone captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_pmdmxvi8gerx4(
// AIX-SAME: ptr noundef readnone captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// AIX-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_pmdmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -54,19 +54,19 @@ void test_pmdmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector unsigne
// CHECK-LABEL: define dso_local void @test_dmxvi8gerx4pp(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]])
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxvi8gerx4pp(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]])
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -79,19 +79,19 @@ void test_dmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigne
// CHECK-LABEL: define dso_local void @test_pmdmxvi8gerx4pp(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_pmdmxvi8gerx4pp(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_pmdmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -104,19 +104,19 @@ void test_pmdmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector unsig
// CHECK-LABEL: define dso_local void @test_dmxvi8gerx4spp(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]])
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxvi8gerx4spp(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]])
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -129,19 +129,19 @@ void test_dmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector unsign
// CHECK-LABEL: define dso_local void @test_pmdmxvi8gerx4spp(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_pmdmxvi8gerx4spp(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], ptr noundef readonly captures(none) [[VPP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA6]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP]], align 32, !tbaa [[__VECTOR_PAIR_TBAA5]]
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_pmdmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
@@ -185,7 +185,7 @@ void test_dmf_basic(char *p, char *res1, char *res2) {
// CHECK-LABEL: define dso_local void @test_dmf_basic2(
// CHECK-SAME: ptr noundef readonly captures(none) [[P1:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RES1:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RES2:%.*]], ptr noundef readonly captures(none) [[V:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[V]], align 16, !tbaa [[CHAR_TBAA10:![0-9]+]]
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[V]], align 16, !tbaa [[CHAR_TBAA9:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.build.dmr(<16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]])
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RES2]], align 128
// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[P1]], align 128
@@ -195,7 +195,7 @@ void test_dmf_basic(char *p, char *res1, char *res2) {
// AIX-LABEL: define void @test_dmf_basic2(
// AIX-SAME: ptr noundef readonly captures(none) [[P1:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RES1:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RES2:%.*]], ptr noundef readonly captures(none) [[V:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[V]], align 16, !tbaa [[CHAR_TBAA10:![0-9]+]]
// AIX-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[V]], align 16, !tbaa [[CHAR_TBAA9:![0-9]+]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.build.dmr(<16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]], <16 x i8> [[TMP0]])
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RES2]], align 128
// AIX-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[P1]], align 128
@@ -212,19 +212,19 @@ void test_dmf_basic2(char *p1, char *res1, char *res2,
// CHECK-LABEL: define dso_local void @test_dmsha2hash(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 1)
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmsha2hash(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 1)
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmsha2hash(unsigned char *vdmrp1, unsigned char *vdmrp2, unsigned char *resp) {
@@ -237,17 +237,17 @@ void test_dmsha2hash(unsigned char *vdmrp1, unsigned char *vdmrp2, unsigned char
// CHECK-LABEL: define dso_local void @test_dmsha3hash(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA11:![0-9]+]]
// CHECK-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA10:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 4)
// CHECK-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA11]]
// CHECK-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmsha3hash(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA11:![0-9]+]]
// AIX-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA10:![0-9]+]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 4)
// AIX-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA11]]
// AIX-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// AIX-NEXT: ret void
//
void test_dmsha3hash(unsigned char *vdmrpp, unsigned char *resp) {
@@ -259,17 +259,17 @@ void test_dmsha3hash(unsigned char *vdmrpp, unsigned char *resp) {
// CHECK-LABEL: define dso_local void @test_dmxxshapad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 2, i32 1, i32 5)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxshapad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 2, i32 1, i32 5)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA8]]
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxshapad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
@@ -277,24 +277,294 @@ void test_dmxxshapad(unsigned char *vdmrp, vector unsigned char vc, unsigned cha
__builtin_mma_dmxxshapad(&vdmr, vc, 2, 1, 5);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmsha256hash(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmsha256hash(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmsha256hash(unsigned char *vdmrp1, unsigned char *vdmrp2, unsigned char *resp) {
__dmr1024 vdmr1 = *((__dmr1024 *)vdmrp1);
__dmr1024 vdmr2 = *((__dmr1024 *)vdmrp2);
__builtin_dmsha256hash(&vdmr1, &vdmr2);
*((__dmr1024 *)resp) = vdmr1;
}
// CHECK-LABEL: define dso_local void @test_dmsha512hash(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 1)
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmsha512hash(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP1:%.*]], ptr noundef readonly captures(none) [[VDMRP2:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP1]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[VDMRP2]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> [[TMP0]], <1024 x i1> [[TMP1]], i32 1)
// AIX-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmsha512hash(unsigned char *vdmrp1, unsigned char *vdmrp2, unsigned char *resp) {
__dmr1024 vdmr1 = *((__dmr1024 *)vdmrp1);
__dmr1024 vdmr2 = *((__dmr1024 *)vdmrp2);
__builtin_dmsha512hash(&vdmr1, &vdmr2);
*((__dmr1024 *)resp) = vdmr1;
}
// CHECK-LABEL: define dso_local void @test_dmsha3dw(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 0)
// CHECK-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmsha3dw(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 0)
// AIX-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// AIX-NEXT: ret void
//
void test_dmsha3dw(unsigned char *vdmrpp, unsigned char *resp) {
__dmr2048 vdmrp = *((__dmr2048 *)vdmrpp);
__builtin_dmsha3dw(&vdmrp);
*((__dmr2048 *)resp) = vdmrp;
}
// CHECK-LABEL: define dso_local void @test_dmcryshash(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 12)
// CHECK-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmcryshash(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRPP:%.*]], ptr noundef writeonly captures(none) initializes((0, 256)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <2048 x i1>, ptr [[VDMRPP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> [[TMP0]], i32 12)
// AIX-NEXT: store <2048 x i1> [[TMP1]], ptr [[RESP]], align 256, !tbaa [[__DMR2048_TBAA10]]
// AIX-NEXT: ret void
//
void test_dmcryshash(unsigned char *vdmrpp, unsigned char *resp) {
__dmr2048 vdmrp = *((__dmr2048 *)vdmrpp);
__builtin_dmcryshash(&vdmrp);
*((__dmr2048 *)resp) = vdmrp;
}
// CHECK-LABEL: define dso_local void @test_dmxxsha3512pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxsha3512pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxsha3512pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxsha3512pad(&vdmr, vc, 0);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmxxsha3384pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 1, i32 1)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxsha3384pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 1, i32 1)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxsha3384pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxsha3384pad(&vdmr, vc, 1);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmxxsha3256pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 0, i32 2)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxsha3256pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 0, i32 2)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxsha3256pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxsha3256pad(&vdmr, vc, 0);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmxxsha3224pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 1, i32 3)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxsha3224pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 0, i32 1, i32 3)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxsha3224pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxsha3224pad(&vdmr, vc, 1);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmxxshake256pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 1, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxshake256pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 1, i32 0, i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxshake256pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxshake256pad(&vdmr, vc, 0);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmxxshake128pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 1, i32 1, i32 1)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxshake128pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 1, i32 1, i32 1)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxshake128pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxshake128pad(&vdmr, vc, 1);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmxxsha384512pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 2, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxsha384512pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 2, i32 0, i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxsha384512pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxsha384512pad(&vdmr, vc);
*((__dmr1024 *)resp) = vdmr;
}
// CHECK-LABEL: define dso_local void @test_dmxxsha224256pad(
// CHECK-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 3, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// CHECK-NEXT: ret void
//
// AIX-LABEL: define void @test_dmxxsha224256pad(
// AIX-SAME: ptr noundef readonly captures(none) [[VDMRP:%.*]], <16 x i8> noundef [[VC:%.*]], ptr noundef writeonly captures(none) initializes((0, 128)) [[RESP:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AIX-NEXT: [[ENTRY:.*:]]
// AIX-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> [[TMP0]], <16 x i8> [[VC]], i32 3, i32 0, i32 0)
// AIX-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP]], align 128, !tbaa [[__DMR1024_TBAA7]]
// AIX-NEXT: ret void
//
void test_dmxxsha224256pad(unsigned char *vdmrp, vector unsigned char vc, unsigned char *resp) {
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__builtin_dmxxsha224256pad(&vdmr, vc);
*((__dmr1024 *)resp) = vdmr;
}
//.
// CHECK: [[META4:![0-9]+]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
// CHECK: [[META5]] = !{!"Simple C/C++ TBAA"}
// CHECK: [[__VECTOR_PAIR_TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
// CHECK: [[META7]] = !{!"__vector_pair", [[META4]], i64 0}
// CHECK: [[__DMR1024_TBAA8]] = !{[[META9:![0-9]+]], [[META9]], i64 0}
// CHECK: [[META9]] = !{!"__dmr1024", [[META4]], i64 0}
// CHECK: [[CHAR_TBAA10]] = !{[[META4]], [[META4]], i64 0}
// CHECK: [[__DMR2048_TBAA11]] = !{[[META12:![0-9]+]], [[META12]], i64 0}
// CHECK: [[META12]] = !{!"__dmr2048", [[META4]], i64 0}
// CHECK: [[META3:![0-9]+]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
// CHECK: [[META4]] = !{!"Simple C/C++ TBAA"}
// CHECK: [[__VECTOR_PAIR_TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
// CHECK: [[META6]] = !{!"__vector_pair", [[META3]], i64 0}
// CHECK: [[__DMR1024_TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
// CHECK: [[META8]] = !{!"__dmr1024", [[META3]], i64 0}
// CHECK: [[CHAR_TBAA9]] = !{[[META3]], [[META3]], i64 0}
// CHECK: [[__DMR2048_TBAA10]] = !{[[META11:![0-9]+]], [[META11]], i64 0}
// CHECK: [[META11]] = !{!"__dmr2048", [[META3]], i64 0}
//.
// AIX: [[META4:![0-9]+]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
// AIX: [[META5]] = !{!"Simple C/C++ TBAA"}
// AIX: [[__VECTOR_PAIR_TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
// AIX: [[META7]] = !{!"__vector_pair", [[META4]], i64 0}
// AIX: [[__DMR1024_TBAA8]] = !{[[META9:![0-9]+]], [[META9]], i64 0}
// AIX: [[META9]] = !{!"__dmr1024", [[META4]], i64 0}
// AIX: [[CHAR_TBAA10]] = !{[[META4]], [[META4]], i64 0}
// AIX: [[__DMR2048_TBAA11]] = !{[[META12:![0-9]+]], [[META12]], i64 0}
// AIX: [[META12]] = !{!"__dmr2048", [[META4]], i64 0}
// AIX: [[META3:![0-9]+]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
// AIX: [[META4]] = !{!"Simple C/C++ TBAA"}
// AIX: [[__VECTOR_PAIR_TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
// AIX: [[META6]] = !{!"__vector_pair", [[META3]], i64 0}
// AIX: [[__DMR1024_TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
// AIX: [[META8]] = !{!"__dmr1024", [[META3]], i64 0}
// AIX: [[CHAR_TBAA9]] = !{[[META3]], [[META3]], i64 0}
// AIX: [[__DMR2048_TBAA10]] = !{[[META11:![0-9]+]], [[META11]], i64 0}
// AIX: [[META11]] = !{!"__dmr2048", [[META3]], i64 0}
//.

24
clang/test/CodeGen/PowerPC/ppc-dmf-mma-builtin-err.c
View File

@@ -28,6 +28,18 @@ void test_mma(unsigned char *vdmrpp, unsigned char *vdmrp, unsigned char *vpp, v
__builtin_mma_dmsha2hash(&vdmr, &vdmr, 0);
__builtin_mma_dmsha3hash(&vdmrpair, 0);
__builtin_mma_dmxxshapad(&vdmr, vc, 0, 0, 0);
__builtin_dmsha256hash(&vdmr, &vdmr);
__builtin_dmsha512hash(&vdmr, &vdmr);
__builtin_dmsha3dw(&vdmrpair);
__builtin_dmcryshash(&vdmrpair);
__builtin_dmxxsha3512pad(&vdmr, vc, 0);
__builtin_dmxxsha3384pad(&vdmr, vc, 0);
__builtin_dmxxsha3256pad(&vdmr, vc, 0);
__builtin_dmxxsha3224pad(&vdmr, vc, 0);
__builtin_dmxxshake256pad(&vdmr, vc, 0);
__builtin_dmxxshake128pad(&vdmr, vc, 0);
__builtin_dmxxsha384512pad(&vdmr, vc);
__builtin_dmxxsha224256pad(&vdmr, vc);
// CHECK: error: '__builtin_mma_dmxvi8gerx4' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4' needs target feature mma,paired-vector-memops
@@ -43,6 +55,18 @@ void test_mma(unsigned char *vdmrpp, unsigned char *vdmrp, unsigned char *vpp, v
// CHECK: error: '__builtin_mma_dmsha2hash' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_mma_dmsha3hash' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_mma_dmxxshapad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmsha256hash' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmsha512hash' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmsha3dw' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmcryshash' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxsha3512pad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxsha3384pad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxsha3256pad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxsha3224pad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxshake256pad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxshake128pad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxsha384512pad' needs target feature mma,isa-future-instructions
// CHECK: error: '__builtin_dmxxsha224256pad' needs target feature mma,isa-future-instructions
// DMF VSX Vector bfloat16 GER 2x builtins.

30
clang/test/Sema/builtins-ppc-crypto.c Normal file
View File

@@ -0,0 +1,30 @@
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu future \
// RUN: -fsyntax-only -verify %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
// RUN: -fsyntax-only -verify %s
void test_crypto(unsigned char *vdmrpp, unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc) {
__dmr2048 vdmrpair = *((__dmr2048 *)vdmrpp);
__dmr1024 vdmr = *((__dmr1024 *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
int ia;
__builtin_dmxxsha3512pad(&vdmr, vc, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
__builtin_dmxxsha3512pad(&vdmr, vc, ia); // expected-error {{argument to '__builtin_dmxxsha3512pad' must be a constant integer}}
__builtin_dmxxsha3384pad(&vdmr, vc, 3); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
__builtin_dmxxsha3384pad(&vdmr, vc, ia); // expected-error {{argument to '__builtin_dmxxsha3384pad' must be a constant integer}}
__builtin_dmxxsha3256pad(&vdmr, vc, -1); // expected-error {{argument value -1 is outside the valid range [0, 1]}}
__builtin_dmxxsha3256pad(&vdmr, vc, ia); // expected-error {{argument to '__builtin_dmxxsha3256pad' must be a constant integer}}
__builtin_dmxxsha3224pad(&vdmr, vc, 4); // expected-error {{argument value 4 is outside the valid range [0, 1]}}
__builtin_dmxxsha3224pad(&vdmr, vc, ia); // expected-error {{argument to '__builtin_dmxxsha3224pad' must be a constant integer}}
__builtin_dmxxshake256pad(&vdmr, vc, -2); // expected-error {{argument value -2 is outside the valid range [0, 1]}}
__builtin_dmxxshake256pad(&vdmr, vc, ia); // expected-error {{argument to '__builtin_dmxxshake256pad' must be a constant integer}}
__builtin_dmxxshake128pad(&vdmr, vc, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
__builtin_dmxxshake128pad(&vdmr, vc, ia); // expected-error {{argument to '__builtin_dmxxshake128pad' must be a constant integer}}
}

536
llvm/test/CodeGen/PowerPC/mmaplus-crypto.ll
View File

@@ -174,3 +174,539 @@ entry:
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmsha512hash(ptr %vop, ptr %vinp, ptr %resp) {
; CHECK-LABEL: test_dmsha512hash:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxvp vsp40, 0(r4)
; CHECK-NEXT: lxvp vsp42, 32(r4)
; CHECK-NEXT: lxvp vsp44, 64(r4)
; CHECK-NEXT: lxvp vsp46, 96(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp42, vsp40, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp46, vsp44, 0
; CHECK-NEXT: dmsha512hash dmr0, dmr1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmsha512hash:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxvp vsp40, 96(r4)
; CHECK-BE-NEXT: lxvp vsp42, 64(r4)
; CHECK-BE-NEXT: lxvp vsp44, 32(r4)
; CHECK-BE-NEXT: lxvp vsp46, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp42, vsp40, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp46, vsp44, 0
; CHECK-BE-NEXT: dmsha512hash dmr0, dmr1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vop, align 64
%1 = load <1024 x i1>, ptr %vinp, align 64
%3 = tail call <1024 x i1> @llvm.ppc.mma.dmsha2hash(<1024 x i1> %0, <1024 x i1> %1, i32 1)
store <1024 x i1> %3, ptr %resp, align 64
ret void
}
define dso_local void @test_dmsha3dw(ptr %vopp, ptr %resp) {
; CHECK-LABEL: test_dmsha3dw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxvp vsp40, 128(r3)
; CHECK-NEXT: lxvp vsp42, 160(r3)
; CHECK-NEXT: lxvp vsp44, 192(r3)
; CHECK-NEXT: lxvp vsp46, 224(r3)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp38, vsp32, 0
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp42, vsp40, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp46, vsp44, 0
; CHECK-NEXT: dmsha3dw dmrp0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 224(r4)
; CHECK-NEXT: stxvp vsp36, 192(r4)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 160(r4)
; CHECK-NEXT: stxvp vsp36, 128(r4)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0
; CHECK-NEXT: stxvp vsp34, 96(r4)
; CHECK-NEXT: stxvp vsp36, 64(r4)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1
; CHECK-NEXT: stxvp vsp34, 32(r4)
; CHECK-NEXT: stxvp vsp36, 0(r4)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmsha3dw:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 224(r3)
; CHECK-BE-NEXT: lxvp vsp36, 192(r3)
; CHECK-BE-NEXT: lxvp vsp32, 160(r3)
; CHECK-BE-NEXT: lxvp vsp38, 128(r3)
; CHECK-BE-NEXT: lxvp vsp40, 96(r3)
; CHECK-BE-NEXT: lxvp vsp42, 64(r3)
; CHECK-BE-NEXT: lxvp vsp44, 32(r3)
; CHECK-BE-NEXT: lxvp vsp46, 0(r3)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp42, vsp40, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp46, vsp44, 0
; CHECK-BE-NEXT: dmsha3dw dmrp0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1
; CHECK-BE-NEXT: stxvp vsp36, 224(r4)
; CHECK-BE-NEXT: stxvp vsp34, 192(r4)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0
; CHECK-BE-NEXT: stxvp vsp36, 160(r4)
; CHECK-BE-NEXT: stxvp vsp34, 128(r4)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
; CHECK-BE-NEXT: blr
entry:
%0 = load <2048 x i1>, ptr %vopp, align 64
%2 = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> %0, i32 0)
store <2048 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmcryshash(ptr %vopp, ptr %resp) {
; CHECK-LABEL: test_dmcryshash:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxvp vsp40, 128(r3)
; CHECK-NEXT: lxvp vsp42, 160(r3)
; CHECK-NEXT: lxvp vsp44, 192(r3)
; CHECK-NEXT: lxvp vsp46, 224(r3)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp38, vsp32, 0
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp42, vsp40, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp46, vsp44, 0
; CHECK-NEXT: dmcryshash dmrp0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 224(r4)
; CHECK-NEXT: stxvp vsp36, 192(r4)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 160(r4)
; CHECK-NEXT: stxvp vsp36, 128(r4)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0
; CHECK-NEXT: stxvp vsp34, 96(r4)
; CHECK-NEXT: stxvp vsp36, 64(r4)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1
; CHECK-NEXT: stxvp vsp34, 32(r4)
; CHECK-NEXT: stxvp vsp36, 0(r4)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmcryshash:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 224(r3)
; CHECK-BE-NEXT: lxvp vsp36, 192(r3)
; CHECK-BE-NEXT: lxvp vsp32, 160(r3)
; CHECK-BE-NEXT: lxvp vsp38, 128(r3)
; CHECK-BE-NEXT: lxvp vsp40, 96(r3)
; CHECK-BE-NEXT: lxvp vsp42, 64(r3)
; CHECK-BE-NEXT: lxvp vsp44, 32(r3)
; CHECK-BE-NEXT: lxvp vsp46, 0(r3)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp42, vsp40, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp46, vsp44, 0
; CHECK-BE-NEXT: dmcryshash dmrp0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1
; CHECK-BE-NEXT: stxvp vsp36, 224(r4)
; CHECK-BE-NEXT: stxvp vsp34, 192(r4)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0
; CHECK-BE-NEXT: stxvp vsp36, 160(r4)
; CHECK-BE-NEXT: stxvp vsp34, 128(r4)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
; CHECK-BE-NEXT: blr
entry:
%0 = load <2048 x i1>, ptr %vopp, align 64
%2 = tail call <2048 x i1> @llvm.ppc.mma.dmsha3hash(<2048 x i1> %0, i32 12)
store <2048 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxsha3512pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxsha3512pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxsha3512pad dmr0, vs0, 1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxsha3512pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxsha3512pad dmr0, vs0, 1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 0, i32 1, i32 0)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxsha3384pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxsha3384pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxsha3384pad dmr0, vs0, 1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxsha3384pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxsha3384pad dmr0, vs0, 1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 0, i32 1, i32 1)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxsha3256pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxsha3256pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxsha3256pad dmr0, vs0, 1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxsha3256pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxsha3256pad dmr0, vs0, 1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 0, i32 1, i32 2)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxsha3224pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxsha3224pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxsha3224pad dmr0, vs0, 1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxsha3224pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxsha3224pad dmr0, vs0, 1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 0, i32 1, i32 3)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxshake256pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxshake256pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxshake256pad dmr0, vs0, 1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxshake256pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxshake256pad dmr0, vs0, 1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 1, i32 1, i32 0)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxshake128pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxshake128pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxshake128pad dmr0, vs0, 1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxshake128pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxshake128pad dmr0, vs0, 1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 1, i32 1, i32 1)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxsha384512pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxsha384512pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxsha384512pad dmr0, vs0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxsha384512pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxsha384512pad dmr0, vs0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 2, i32 0, i32 0)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}
define dso_local void @test_dmxxsha224256pad(ptr %vopp, ptr %vcp, ptr %resp) {
; CHECK-LABEL: test_dmxxsha224256pad:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
; CHECK-NEXT: lxvp vsp32, 64(r3)
; CHECK-NEXT: lxvp vsp38, 96(r3)
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: dmxxsha224256pad dmr0, vs0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test_dmxxsha224256pad:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
; CHECK-BE-NEXT: lxvp vsp32, 32(r3)
; CHECK-BE-NEXT: lxvp vsp38, 0(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: dmxxsha224256pad dmr0, vs0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
entry:
%0 = load <1024 x i1>, ptr %vopp, align 64
%1 = load <16 x i8>, ptr %vcp, align 64
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxxshapad(<1024 x i1> %0, <16 x i8> %1, i32 3, i32 0, i32 0)
store <1024 x i1> %2, ptr %resp, align 64
ret void
}