[RISCV] Simplify testcases in zibi.ll. NFC.
Remove unneeded load instructions.
This commit is contained in:
Jim Lin
@@ -4,197 +4,187 @@
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ZIBI,ZIBI-RV64 %s
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define void @test_bne_neg(ptr %b) nounwind {
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define i32 @test_bne_neg(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_bne_neg:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: bnei a1, -1, .LBB0_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB0_2: # %end
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; ZIBI-NEXT: bnei a0, -1, .LBB0_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp ne i32 %val1, -1
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB0_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp ne i32 %a, -1
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_beq_neg(ptr %b) nounwind {
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define i32 @test_beq_neg(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_beq_neg:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: beqi a1, -1, .LBB1_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB1_2: # %end
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; ZIBI-NEXT: beqi a0, -1, .LBB1_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp eq i32 %val1, -1
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB1_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp eq i32 %a, -1
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_bne_zero(ptr %b) nounwind {
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define i32 @test_bne_zero(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_bne_zero:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: bnez a1, .LBB2_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB2_2: # %end
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; ZIBI-NEXT: bnez a0, .LBB2_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp ne i32 %val1, 0
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB2_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp ne i32 %a, 0
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_beq_zero(ptr %b) nounwind {
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define i32 @test_beq_zero(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_beq_zero:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: beqz a1, .LBB3_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB3_2: # %end
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; ZIBI-NEXT: beqz a0, .LBB3_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp eq i32 %val1, 0
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB3_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp eq i32 %a, 0
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_bne_1(ptr %b) nounwind {
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define i32 @test_bne_1(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_bne_1:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: bnei a1, 1, .LBB4_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB4_2: # %end
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; ZIBI-NEXT: bnei a0, 1, .LBB4_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp ne i32 %val1, 1
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB4_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp ne i32 %a, 1
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_beq_1(ptr %b) nounwind {
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define i32 @test_beq_1(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_beq_1:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: beqi a1, 1, .LBB5_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB5_2: # %end
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; ZIBI-NEXT: beqi a0, 1, .LBB5_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp eq i32 %val1, 1
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB5_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp eq i32 %a, 1
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_bne_31(ptr %b) nounwind {
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define i32 @test_bne_31(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_bne_31:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: bnei a1, 31, .LBB6_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB6_2: # %end
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; ZIBI-NEXT: bnei a0, 31, .LBB6_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp ne i32 %val1, 31
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB6_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp ne i32 %a, 31
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_beq_31(ptr %b) nounwind {
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define i32 @test_beq_31(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_beq_31:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: beqi a1, 31, .LBB7_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB7_2: # %end
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; ZIBI-NEXT: beqi a0, 31, .LBB7_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp eq i32 %val1, 31
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB7_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp eq i32 %a, 31
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_bne_32(ptr %b) nounwind {
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define i32 @test_bne_32(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_bne_32:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: li a2, 32
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; ZIBI-NEXT: bne a1, a2, .LBB8_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB8_2: # %end
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; ZIBI-NEXT: li a1, 32
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; ZIBI-NEXT: bne a0, a1, .LBB8_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp ne i32 %val1, 32
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB8_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp ne i32 %a, 32
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define void @test_beq_32(ptr %b) nounwind {
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define i32 @test_beq_32(i32 signext %a) nounwind {
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; ZIBI-LABEL: test_beq_32:
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; ZIBI: # %bb.0:
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; ZIBI-NEXT: lw a1, 0(a0)
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; ZIBI-NEXT: li a2, 32
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; ZIBI-NEXT: beq a1, a2, .LBB9_2
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; ZIBI-NEXT: # %bb.1: # %test2
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; ZIBI-NEXT: lw zero, 0(a0)
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; ZIBI-NEXT: .LBB9_2: # %end
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; ZIBI-NEXT: li a1, 32
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; ZIBI-NEXT: beq a0, a1, .LBB9_2
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; ZIBI-NEXT: # %bb.1: # %f
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; ZIBI-NEXT: li a0, 0
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; ZIBI-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp eq i32 %val1, 32
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br i1 %tst1, label %end, label %test2, !prof !0
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test2:
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%val2 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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; ZIBI-NEXT: .LBB9_2: # %t
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; ZIBI-NEXT: li a0, 1
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; ZIBI-NEXT: ret
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%cmp = icmp eq i32 %a, 32
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br i1 %cmp, label %t, label %f, !prof !0
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f:
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ret i32 0
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t:
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ret i32 1
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}
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!0 = !{!"branch_weights", i32 1, i32 99}
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define i32 @test_select_beq_neg(i32 %a, i32 %b, i32 %c) nounwind {
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