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AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_ds_swizzle (#186024)

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This commit is contained in:
vangthao95
2026-03-13 15:13:50 -07:00
committed by GitHub
parent 7f538fd89f
commit 4e2bb5861d
3 changed files with 79 additions and 9 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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@@ -1580,4 +1580,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_ds_bvh_stack_push8_pop2_rtn}, Standard)
.Div(S64, {{Vgpr64, Vgpr32}, {IntrId, Vgpr32, Vgpr32, VgprV8S32}});
addRulesForIOpcs({amdgcn_ds_swizzle}, Standard)
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32}});
} // end initialize rules

23
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
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@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s
---
name: ds_swizzle_s
@@ -15,8 +14,26 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), [[COPY1]](s32), 0
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), [[COPY1]](s32), 0
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), %0, 0
...
---
name: ds_swizzle_v
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ds_swizzle_v
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), [[COPY]](s32), 0
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), %0, 0
...

61
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
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@@ -1,14 +1,63 @@
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CHECK,GFX7 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CHECK,GFX7 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=CHECK,GFX8 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=CHECK,GFX8 %s
declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0
; CHECK-LABEL: {{^}}ds_swizzle:
; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:swizzle(BITMASK_PERM,"00p11")
define amdgpu_kernel void @ds_swizzle(ptr addrspace(1) %out, i32 %src) nounwind {
; GFX7-LABEL: ds_swizzle:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dword s2, s[4:5], 0xb
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX8-LABEL: ds_swizzle:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: ds_swizzle_b32 v2, v0 offset:swizzle(BITMASK_PERM,"00p11")
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0
store i32 %swizzle, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_ps i32 @ds_swizzle_s(i32 inreg %src) {
; CHECK-LABEL: ds_swizzle_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: ; return to shader part epilog
%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100)
ret i32 %swizzle
}
define amdgpu_ps i32 @ds_swizzle_v(i32 %src) {
; CHECK-LABEL: ds_swizzle_v:
; CHECK: ; %bb.0:
; CHECK-NEXT: ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: ; return to shader part epilog
%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100)
ret i32 %swizzle
}
declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0
attributes #0 = { nounwind readnone convergent }