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[PowerPC] Fix assert which caused by PR 190606 (#194040)

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Fixed assert which caused by
https://github.com/llvm/llvm-project/pull/190606
This commit is contained in:
zhijian lin
2026-04-29 13:55:04 -04:00
committed by GitHub
parent de3ff7e2ac
commit 2a54e8feee
2 changed files with 75 additions and 9 deletions
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19
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@@ -15861,7 +15861,8 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
if (Subtarget.isISA3_1())
return SDValue();
if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
return SDValue();
SDValue N0 = N->getOperand(0);
@@ -15878,20 +15879,20 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDLoc dl(N);
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
SDValue X = isNullConstant(LHS) ? RHS : LHS;
EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.
if ((XVT == MVT::i64 || VT == MVT::i64) && !Subtarget.isPPC64())
return SDValue();
// On PPC64, i32 carry operations use the full 64-bit XER register,
// so we must use i64 operations to avoid incorrect results.
// Use i64 operations and truncate the result if needed.
EVT OpVT = VT;
if (Subtarget.isPPC64() && VT == MVT::i32)
OpVT = MVT::i64;
if (XVT != MVT::i64 && Subtarget.isPPC64())
// Zero-extend if input type is not 64bits.
X = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, X);
// Zero-extend if input type differs from operation type.
if (XVT != OpVT)
X = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, X);
EVT OpVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
// Generate: SUBFE(ADDC(X, -1)).
SDValue MinusOne = DAG.getAllOnesConstant(dl, OpVT);
@@ -15902,7 +15903,7 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
Addc, Addc, Carry);
// Truncate back to i32 if we used i64 operations.
if (OpVT != VT)
if (OpVT == MVT::i64 && VT == MVT::i32)
return DAG.getNode(ISD::TRUNCATE, dl, VT, Sube);
return Sube;

65
llvm/test/CodeGen/PowerPC/test-issue-98598.ll Normal file
View File

@@ -0,0 +1,65 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-32BIT
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-64BIT
define dso_local zeroext range(i8 -1, 1) i8 @f(i8 noundef zeroext %x) {
; CHECK-32BIT-LABEL: f:
; CHECK-32BIT: # %bb.0: # %entry
; CHECK-32BIT-NEXT: addic r3, r3, -1
; CHECK-32BIT-NEXT: subfe r3, r3, r3
; CHECK-32BIT-NEXT: clrlwi r3, r3, 24
; CHECK-32BIT-NEXT: blr
;
; CHECK-64BIT-LABEL: f:
; CHECK-64BIT: # %bb.0: # %entry
; CHECK-64BIT-NEXT: addic r3, r3, -1
; CHECK-64BIT-NEXT: subfe r3, r3, r3
; CHECK-64BIT-NEXT: clrldi r3, r3, 56
; CHECK-64BIT-NEXT: blr
entry:
%cmp = icmp eq i8 %x, 0
%conv2 = sext i1 %cmp to i8
ret i8 %conv2
}
define i32 @compare32(i64 %conv1) {
; CHECK-32BIT-LABEL: compare32:
; CHECK-32BIT: # %bb.0: # %entry
; CHECK-32BIT-NEXT: or r3, r4, r3
; CHECK-32BIT-NEXT: addic r3, r3, -1
; CHECK-32BIT-NEXT: subfe r3, r3, r3
; CHECK-32BIT-NEXT: blr
;
; CHECK-64BIT-LABEL: compare32:
; CHECK-64BIT: # %bb.0: # %entry
; CHECK-64BIT-NEXT: addic r3, r3, -1
; CHECK-64BIT-NEXT: subfe r3, r3, r3
; CHECK-64BIT-NEXT: blr
entry:
%tobool2.not = icmp eq i64 %conv1, 0
%cond = sext i1 %tobool2.not to i32
ret i32 %cond
}
define i64 @compare64(i32 %conv1) {
; CHECK-32BIT-LABEL: compare64:
; CHECK-32BIT: # %bb.0: # %entry
; CHECK-32BIT-NEXT: addic r3, r3, -1
; CHECK-32BIT-NEXT: subfe r3, r3, r3
; CHECK-32BIT-NEXT: mr r4, r3
; CHECK-32BIT-NEXT: blr
;
; CHECK-64BIT-LABEL: compare64:
; CHECK-64BIT: # %bb.0: # %entry
; CHECK-64BIT-NEXT: clrldi r3, r3, 32
; CHECK-64BIT-NEXT: addic r3, r3, -1
; CHECK-64BIT-NEXT: subfe r3, r3, r3
; CHECK-64BIT-NEXT: blr
entry:
%tobool2.not = icmp eq i32 %conv1, 0
%cond = sext i1 %tobool2.not to i64
ret i64 %cond
}