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Make MachineBlockFrequencyInfo a required pass for the MachineScheduler pass. (#176172)

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This is needed to support functionality in the AMDGPU scheduler. Various
passes have been modified to preserve MBFI to ensure that this change
does not introduce new invocations of MBFI. Some targets have passes
reordered, but there are no new runs of MBFI.
This commit is contained in:
Tony Linthicum
2026-01-15 14:26:51 -06:00
committed by GitHub
parent d03ce72f40
commit 15b9109bc7
14 changed files with 65 additions and 18 deletions
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6
llvm/include/llvm/CodeGen/MachineScheduler.h
View File

@@ -82,6 +82,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
@@ -117,6 +118,7 @@ enum Direction {
LLVM_ABI extern cl::opt<MISched::Direction> PreRADirection;
LLVM_ABI extern cl::opt<bool> VerifyScheduling;
#ifndef NDEBUG
extern cl::opt<bool> ViewMISchedDAGs;
extern cl::opt<bool> PrintDAGs;
@@ -147,6 +149,7 @@ struct LLVM_ABI MachineSchedContext {
const TargetMachine *TM = nullptr;
AAResults *AA = nullptr;
LiveIntervals *LIS = nullptr;
MachineBlockFrequencyInfo *MBFI = nullptr;
RegisterClassInfo *RegClassInfo;
@@ -309,6 +312,7 @@ class LLVM_ABI ScheduleDAGMI : public ScheduleDAGInstrs {
protected:
AAResults *AA;
LiveIntervals *LIS;
MachineBlockFrequencyInfo *MBFI;
std::unique_ptr<MachineSchedStrategy> SchedImpl;
/// Ordered list of DAG postprocessing steps.
@@ -330,7 +334,7 @@ public:
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
bool RemoveKillFlags)
: ScheduleDAGInstrs(*C->MF, C->MLI, RemoveKillFlags), AA(C->AA),
LIS(C->LIS), SchedImpl(std::move(S)) {}
LIS(C->LIS), MBFI(C->MBFI), SchedImpl(std::move(S)) {}
// Provide a vtable anchor
~ScheduleDAGMI() override;

11
llvm/lib/CodeGen/MachineScheduler.cpp
View File

@@ -332,6 +332,7 @@ public:
MachineDominatorTree &MDT;
AAResults &AA;
LiveIntervals &LIS;
MachineBlockFrequencyInfo &MBFI;
};
MachineSchedulerImpl() = default;
@@ -415,6 +416,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfoWrapperPass);
INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
@@ -432,6 +434,7 @@ void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -555,6 +558,7 @@ bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
this->TM = &TM;
AA = &Analyses.AA;
LIS = &Analyses.LIS;
MBFI = &Analyses.MBFI;
if (VerifyScheduling) {
LLVM_DEBUG(LIS->dump());
@@ -660,8 +664,9 @@ bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
auto &MBFI = getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
Impl.setLegacyPass(this);
return Impl.run(MF, TM, {MLI, MDT, AA, LIS});
return Impl.run(MF, TM, {MLI, MDT, AA, LIS, MBFI});
}
MachineSchedulerPass::MachineSchedulerPass(const TargetMachine *TM)
@@ -693,8 +698,10 @@ MachineSchedulerPass::run(MachineFunction &MF,
.getManager();
auto &AA = FAM.getResult<AAManager>(MF.getFunction());
auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
auto &MBFI = MFAM.getResult<MachineBlockFrequencyAnalysis>(MF);
Impl->setMFAM(&MFAM);
bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS});
bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS, MBFI});
if (!Changed)
return PreservedAnalyses::all();

6
llvm/lib/CodeGen/MachineSink.cpp
View File

@@ -309,8 +309,10 @@ public:
AU.addPreserved<MachineCycleInfoWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
if (UseBlockFreqInfo)
if (UseBlockFreqInfo) {
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
}
AU.addRequired<TargetPassConfig>();
}
};
@@ -781,6 +783,8 @@ MachineSinkingPass::run(MachineFunction &MF,
auto PA = getMachineFunctionPassPreservedAnalyses();
PA.preserve<MachineCycleAnalysis>();
PA.preserve<MachineLoopAnalysis>();
if (UseBlockFreqInfo)
PA.preserve<MachineBlockFrequencyAnalysis>();
return PA;
}

34
llvm/lib/CodeGen/PHIElimination.cpp
View File

@@ -22,6 +22,8 @@
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineDomTreeUpdater.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -74,6 +76,8 @@ class PHIEliminationImpl {
MachineLoopInfo *MLI = nullptr;
MachineDominatorTree *MDT = nullptr;
MachinePostDominatorTree *PDT = nullptr;
const MachineBranchProbabilityInfo *MBPI = nullptr;
MachineBlockFrequencyInfo *MBFI = nullptr;
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
/// in predecessor basic blocks.
@@ -127,11 +131,18 @@ public:
P->getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>();
auto *PDTWrapper =
P->getAnalysisIfAvailable<MachinePostDominatorTreeWrapperPass>();
auto *MBPIWrapper =
P->getAnalysisIfAvailable<MachineBranchProbabilityInfoWrapperPass>();
auto *MBFIWrapper =
P->getAnalysisIfAvailable<MachineBlockFrequencyInfoWrapperPass>();
LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr;
PDT = PDTWrapper ? &PDTWrapper->getPostDomTree() : nullptr;
MBPI = MBPIWrapper ? &MBPIWrapper->getMBPI() : nullptr;
MBFI = MBFIWrapper ? &MBFIWrapper->getMBFI() : nullptr;
}
PHIEliminationImpl(MachineFunction &MF, MachineFunctionAnalysisManager &AM)
@@ -140,7 +151,9 @@ public:
MLI(AM.getCachedResult<MachineLoopAnalysis>(MF)),
MDT(AM.getCachedResult<MachineDominatorTreeAnalysis>(MF)),
PDT(AM.getCachedResult<MachinePostDominatorTreeAnalysis>(MF)),
MFAM(&AM) {}
MBPI(AM.getCachedResult<MachineBranchProbabilityAnalysis>(MF)),
MBFI(AM.getCachedResult<MachineBlockFrequencyAnalysis>(MF)), MFAM(&AM) {
}
bool run(MachineFunction &MF);
};
@@ -181,6 +194,7 @@ PHIEliminationPass::run(MachineFunction &MF,
PA.preserve<MachineDominatorTreeAnalysis>();
PA.preserve<MachinePostDominatorTreeAnalysis>();
PA.preserve<MachineLoopAnalysis>();
PA.preserve<MachineBlockFrequencyAnalysis>();
return PA;
}
@@ -196,6 +210,8 @@ INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
"Eliminate PHI nodes for register allocation", false,
false)
INITIALIZE_PASS_DEPENDENCY(LiveVariablesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfoWrapperPass)
INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
"Eliminate PHI nodes for register allocation", false, false)
@@ -208,6 +224,7 @@ void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addPreserved<MachinePostDominatorTreeWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -830,11 +847,22 @@ bool PHIEliminationImpl::SplitPHIEdges(
}
if (!ShouldSplit && !SplitAllCriticalEdges)
continue;
if (!(P ? PreMBB->SplitCriticalEdge(&MBB, *P, LiveInSets, &MDTU)
: PreMBB->SplitCriticalEdge(&MBB, *MFAM, LiveInSets, &MDTU))) {
MachineBasicBlock *NewBB;
if (P)
NewBB = PreMBB->SplitCriticalEdge(&MBB, *P, LiveInSets, &MDTU);
else
NewBB = PreMBB->SplitCriticalEdge(&MBB, *MFAM, LiveInSets, &MDTU);
if (!NewBB) {
LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
continue;
}
// Patch up MBFI after split if it is available.
if (MBFI) {
assert(MBPI);
MBFI->onEdgeSplit(*PreMBB, *NewBB, *MBPI);
}
Changed = true;
++NumCriticalEdgesSplit;
}

7
llvm/lib/CodeGen/UnreachableBlockElim.cpp
View File

@@ -23,6 +23,7 @@
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -52,6 +53,7 @@ public:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addPreserved<DominatorTreeWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
}
};
}
@@ -70,6 +72,7 @@ PreservedAnalyses UnreachableBlockElimPass::run(Function &F,
return PreservedAnalyses::all();
PreservedAnalyses PA;
PA.preserve<DominatorTreeAnalysis>();
PA.preserve<MachineBlockFrequencyAnalysis>();
return PA;
}
@@ -111,6 +114,7 @@ void UnreachableMachineBlockElimLegacy::getAnalysisUsage(
AU.addPreserved<MachineLoopInfoWrapperPass>();
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addPreserved<MachinePostDominatorTreeWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -127,7 +131,8 @@ UnreachableMachineBlockElimPass::run(MachineFunction &MF,
return getMachineFunctionPassPreservedAnalyses()
.preserve<MachineLoopAnalysis>()
.preserve<MachineDominatorTreeAnalysis>()
.preserve<MachinePostDominatorTreeAnalysis>();
.preserve<MachinePostDominatorTreeAnalysis>()
.preserve<MachineBlockFrequencyAnalysis>();
}
bool UnreachableMachineBlockElimLegacy::runOnMachineFunction(

3
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
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@@ -56,6 +56,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachinePostDominators.h"
@@ -160,6 +161,7 @@ public:
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveVariablesWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
@@ -880,5 +882,6 @@ SILowerControlFlowPass::run(MachineFunction &MF,
PA.preserve<SlotIndexesAnalysis>();
PA.preserve<LiveIntervalsAnalysis>();
PA.preserve<LiveVariablesAnalysis>();
PA.preserve<MachineBlockFrequencyAnalysis>();
return PA;
}

2
llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
View File

@@ -17,6 +17,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -353,6 +354,7 @@ public:
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
};

1
llvm/test/CodeGen/AArch64/O3-pipeline.ll
View File

@@ -178,7 +178,6 @@
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: AArch64 Post Coalescer pass
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Debug Variable Analysis
; CHECK-NEXT: Live Stack Slot Analysis
; CHECK-NEXT: Virtual Register Map

3
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
View File

@@ -656,7 +656,6 @@
; GCN-O1-OPTS-NEXT: GCN DPP Combine
; GCN-O1-OPTS-NEXT: SI Load Store Optimizer
; GCN-O1-OPTS-NEXT: SI Peephole SDWA
; GCN-O1-OPTS-NEXT: Machine Block Frequency Analysis
; GCN-O1-OPTS-NEXT: MachineDominator Tree Construction
; GCN-O1-OPTS-NEXT: Early Machine Loop Invariant Code Motion
; GCN-O1-OPTS-NEXT: MachineDominator Tree Construction
@@ -981,7 +980,6 @@
; GCN-O2-NEXT: GCN DPP Combine
; GCN-O2-NEXT: SI Load Store Optimizer
; GCN-O2-NEXT: SI Peephole SDWA
; GCN-O2-NEXT: Machine Block Frequency Analysis
; GCN-O2-NEXT: MachineDominator Tree Construction
; GCN-O2-NEXT: Early Machine Loop Invariant Code Motion
; GCN-O2-NEXT: MachineDominator Tree Construction
@@ -1320,7 +1318,6 @@
; GCN-O3-NEXT: GCN DPP Combine
; GCN-O3-NEXT: SI Load Store Optimizer
; GCN-O3-NEXT: SI Peephole SDWA
; GCN-O3-NEXT: Machine Block Frequency Analysis
; GCN-O3-NEXT: MachineDominator Tree Construction
; GCN-O3-NEXT: Early Machine Loop Invariant Code Motion
; GCN-O3-NEXT: MachineDominator Tree Construction

2
llvm/test/CodeGen/ARM/O3-pipeline.ll
View File

@@ -128,8 +128,8 @@
; CHECK-NEXT: Live Interval Analysis
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Debug Variable Analysis
; CHECK-NEXT: Live Stack Slot Analysis
; CHECK-NEXT: Virtual Register Map

1
llvm/test/CodeGen/LoongArch/opt-pipeline.ll
View File

@@ -126,7 +126,6 @@
; LAXX-NEXT: Rename Disconnected Subregister Components
; LAXX-NEXT: Machine Instruction Scheduler
; LAXX-NEXT: LoongArch Dead register definitions
; LAXX-NEXT: Machine Block Frequency Analysis
; LAXX-NEXT: Debug Variable Analysis
; LAXX-NEXT: Live Stack Slot Analysis
; LAXX-NEXT: Virtual Register Map

4
llvm/test/CodeGen/PowerPC/O3-pipeline.ll
View File

@@ -164,12 +164,12 @@
; CHECK-NEXT: Live Interval Analysis
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: PowerPC VSX FMA Mutation
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Debug Variable Analysis
; CHECK-NEXT: Live Stack Slot Analysis
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: Virtual Register Map
; CHECK-NEXT: Live Register Matrix
; CHECK-NEXT: Bundle Machine CFG Edges

1
llvm/test/CodeGen/RISCV/O3-pipeline.ll
View File

@@ -144,7 +144,6 @@
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Debug Variable Analysis
; CHECK-NEXT: Live Stack Slot Analysis
; CHECK-NEXT: Virtual Register Map

2
llvm/test/CodeGen/X86/opt-pipeline.ll
View File

@@ -145,8 +145,8 @@
; CHECK-NEXT: Live Interval Analysis
; CHECK-NEXT: Register Coalescer
; CHECK-NEXT: Rename Disconnected Subregister Components
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Machine Instruction Scheduler
; CHECK-NEXT: Debug Variable Analysis
; CHECK-NEXT: Live Stack Slot Analysis
; CHECK-NEXT: Virtual Register Map