86b9775612
These should use O2 with the optsize or minsize attributes instead. This enforces that there is no divergence between pipeline-level Os/Oz and function-level Os/Oz at an architectural level. For the purpose of testing IR that does not have optsize/minsize itself, it's possible to use `-force-attribute=optsize` etc.
92 lines
6.0 KiB
LLVM
92 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -O2 -S %s -o - | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
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target triple = "arm64e-apple-ios19.0.0"
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; This test checks if we generate a phi for the <vscale 16 x float> value or we manage
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; to promote it during inlining.
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; Function Attrs: mustprogress optsize ssp uwtable(sync)
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define void @pluto() #0 {
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; CHECK-LABEL: define void @pluto(
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; CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 48 to ptr), align 16
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i64 [[TMP1]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = tail call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> zeroinitializer, <vscale x 4 x float> zeroinitializer, i64 0)
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; CHECK-NEXT: br label %[[SNORK_EXIT:.*]]
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; CHECK: [[SNORK_EXIT]]:
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; CHECK-NEXT: [[DOT0:%.*]] = phi <vscale x 16 x float> [ undef, [[TMP0:%.*]] ], [ [[SPEC_SELECT:%.*]], %[[SNORK_EXIT]] ]
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; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP2]], <vscale x 16 x float> [[TMP3]], <vscale x 16 x float> [[DOT0]]
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; CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SPEC_SELECT]], i64 0)
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; CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv4f32(i32 0, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> [[TMP4]])
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; CHECK-NEXT: br label %[[SNORK_EXIT]]
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;
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br label %1
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1: ; preds = %1, %0
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call void @ham() #5
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br label %1
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}
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; Function Attrs: alwaysinline mustprogress optsize ssp uwtable(sync)
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define void @ham() #1 {
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; CHECK-LABEL: define void @ham(
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; CHECK-SAME: ) local_unnamed_addr #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: [[SNORK_EXIT:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 48 to ptr), align 16
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[TMP0]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> undef, i64 0)
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; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> [[TMP2]]
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; CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv4f32(i32 0, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> [[TMP3]])
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; CHECK-NEXT: ret void
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;
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%1 = alloca <vscale x 16 x float>, align 16
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%2 = load i64, ptr inttoptr (i64 48 to ptr), align 8
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%3 = call i64 @snork(i64 noundef %2, ptr noundef nonnull align 16 %1) #5
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%4 = load <vscale x 16 x float>, ptr %1, align 16
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%5 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %4, i64 0)
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call void @llvm.aarch64.sme.mopa.nxv4f32(i32 0, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> %5)
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ret void
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float>, <vscale x 4 x float>, i64 immarg) #2
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; Function Attrs: alwaysinline mustprogress nounwind optsize ssp uwtable(sync)
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define i64 @snork(i64 noundef %0, ptr noundef nonnull align 16 %1) #3 {
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; CHECK-LABEL: define noundef i64 @snork(
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; CHECK-SAME: i64 noundef [[TMP0:%.*]], ptr noundef nonnull writeonly align 16 captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR3:[0-9]+]] {
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; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i64 [[TMP0]], 0
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; CHECK-NEXT: br i1 [[TMP3]], label %[[BB4:.*]], label %[[BB6:.*]]
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; CHECK: [[BB4]]:
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; CHECK-NEXT: [[TMP5:%.*]] = tail call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> zeroinitializer, <vscale x 4 x float> zeroinitializer, i64 0)
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; CHECK-NEXT: store <vscale x 16 x float> [[TMP5]], ptr [[TMP1]], align 16
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; CHECK-NEXT: br label %[[BB6]]
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; CHECK: [[BB6]]:
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; CHECK-NEXT: ret i64 0
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;
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%3 = icmp sgt i64 %0, 0
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br i1 %3, label %4, label %6
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4: ; preds = %2
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%5 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> zeroinitializer, <vscale x 4 x float> zeroinitializer, i64 0)
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store <vscale x 16 x float> %5, ptr %1, align 16
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br label %6
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6: ; preds = %4, %2
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ret i64 0
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #2
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; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
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declare void @llvm.aarch64.sme.mopa.nxv4f32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #4
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attributes #0 = { mustprogress optsize ssp uwtable(sync) "aarch64_new_za" "aarch64_pstate_sm_enabled" "frame-pointer"="non-leaf" "no-builtin-calloc" "no-builtin-stpcpy" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" }
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attributes #1 = { alwaysinline mustprogress optsize ssp uwtable(sync) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "frame-pointer"="non-leaf" "no-builtin-calloc" "no-builtin-stpcpy" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" }
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attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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attributes #3 = { alwaysinline mustprogress nounwind optsize ssp uwtable(sync) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "frame-pointer"="non-leaf" "no-builtin-calloc" "no-builtin-stpcpy" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" }
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attributes #4 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) }
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attributes #5 = { optsize "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-builtin-calloc" "no-builtin-stpcpy" }
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