184f236a18
The fix does the following in expandPartwordCmpXchg and insertRMWCmpXchgLoop. - Issues volatile operations in the emulation loops if the original operation is volatile. - A preheader load is used for initializing the "cmp" and "new" values of the cmpxchg in the loop. Makes this load atomic. This is done under a target hook (`issueAtomicInitLoadForAtomicEmulation()`) , to allow backends to migrate independently. - `processAtomicInstr` is called on this load, to massage it into something that can be lowered in SelectionDAG / GISel. - This caused 3 kinds of failures. 1. Caused by change to codegen: updated these either using the scripts, or mechanically (using claude) to match the new codegen. 2. Crashes caused by newly created atomic loads not being processed by AtomicExpandPass. (The atomic load if tested in an independent test does not cause a crash). To fix these, added recursive calls to processAtomicInstr on the newly created atomic loads. These calls convert the loads to libcalls, or cast them to integer types. 3. Crashes in X86, AMDGPU, and AArch64 caused by unhandled vector types. These loads crash even with upstream LLVM, due to the lack of support in these targets for vector atomic loads (the corresponding vector atomicrmw instructions are supported). Disabled issuing atomic loads for these backends. Will follow up with individual PRs to revert to default behavior.
94 lines
3.3 KiB
LLVM
94 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-unknown \
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; RUN: < %s | FileCheck --check-prefix=CHECK-64 %s
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; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc-unknown-unknown \
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; RUN: < %s | FileCheck --check-prefix=CHECK-32 %s
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define float @test_add(ptr %ptr, float %incr) {
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; CHECK-64-LABEL: test_add:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: sync
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; CHECK-64-NEXT: lwz 4, 0(3)
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; CHECK-64-NEXT: stw 4, -4(1)
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; CHECK-64-NEXT: lfs 0, -4(1)
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; CHECK-64-NEXT: .LBB0_1: # %atomicrmw.start
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; CHECK-64-NEXT: # =>This Loop Header: Depth=1
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; CHECK-64-NEXT: # Child Loop BB0_2 Depth 2
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; CHECK-64-NEXT: fadds 2, 0, 1
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; CHECK-64-NEXT: stfs 2, -8(1)
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; CHECK-64-NEXT: stfs 0, -12(1)
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; CHECK-64-NEXT: lwz 5, -8(1)
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; CHECK-64-NEXT: lwz 6, -12(1)
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; CHECK-64-NEXT: .LBB0_2: # %cmpxchg.start
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; CHECK-64-NEXT: # Parent Loop BB0_1 Depth=1
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; CHECK-64-NEXT: # => This Inner Loop Header: Depth=2
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; CHECK-64-NEXT: lwarx 4, 0, 3
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; CHECK-64-NEXT: cmplw 4, 6
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; CHECK-64-NEXT: bne- 0, .LBB0_5
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; CHECK-64-NEXT: # %bb.3: # %cmpxchg.fencedstore
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; CHECK-64-NEXT: #
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; CHECK-64-NEXT: stwcx. 5, 0, 3
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; CHECK-64-NEXT: creqv 20, 20, 20
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; CHECK-64-NEXT: bne- 0, .LBB0_2
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; CHECK-64-NEXT: .LBB0_4: # %cmpxchg.end
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; CHECK-64-NEXT: #
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; CHECK-64-NEXT: stw 4, -16(1)
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; CHECK-64-NEXT: lfs 0, -16(1)
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; CHECK-64-NEXT: bc 4, 20, .LBB0_1
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; CHECK-64-NEXT: b .LBB0_6
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; CHECK-64-NEXT: .LBB0_5: # %cmpxchg.nostore
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; CHECK-64-NEXT: #
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; CHECK-64-NEXT: crxor 20, 20, 20
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; CHECK-64-NEXT: b .LBB0_4
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; CHECK-64-NEXT: .LBB0_6: # %atomicrmw.end
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; CHECK-64-NEXT: fmr 1, 0
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; CHECK-64-NEXT: lwsync
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test_add:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: stwu 1, -32(1)
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; CHECK-32-NEXT: .cfi_def_cfa_offset 32
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; CHECK-32-NEXT: sync
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; CHECK-32-NEXT: lwz 4, 0(3)
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; CHECK-32-NEXT: stw 4, 28(1)
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; CHECK-32-NEXT: lfs 0, 28(1)
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; CHECK-32-NEXT: .LBB0_1: # %atomicrmw.start
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; CHECK-32-NEXT: # =>This Loop Header: Depth=1
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; CHECK-32-NEXT: # Child Loop BB0_2 Depth 2
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; CHECK-32-NEXT: fadds 2, 0, 1
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; CHECK-32-NEXT: stfs 2, 24(1)
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; CHECK-32-NEXT: stfs 0, 20(1)
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; CHECK-32-NEXT: lwz 5, 24(1)
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; CHECK-32-NEXT: lwz 6, 20(1)
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; CHECK-32-NEXT: .LBB0_2: # %cmpxchg.start
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; CHECK-32-NEXT: # Parent Loop BB0_1 Depth=1
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; CHECK-32-NEXT: # => This Inner Loop Header: Depth=2
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; CHECK-32-NEXT: lwarx 4, 0, 3
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; CHECK-32-NEXT: cmplw 4, 6
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; CHECK-32-NEXT: bne- 0, .LBB0_5
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; CHECK-32-NEXT: # %bb.3: # %cmpxchg.fencedstore
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; CHECK-32-NEXT: #
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; CHECK-32-NEXT: stwcx. 5, 0, 3
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; CHECK-32-NEXT: creqv 20, 20, 20
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; CHECK-32-NEXT: bne- 0, .LBB0_2
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; CHECK-32-NEXT: .LBB0_4: # %cmpxchg.end
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; CHECK-32-NEXT: #
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; CHECK-32-NEXT: stw 4, 16(1)
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; CHECK-32-NEXT: lfs 0, 16(1)
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; CHECK-32-NEXT: bc 4, 20, .LBB0_1
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; CHECK-32-NEXT: b .LBB0_6
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; CHECK-32-NEXT: .LBB0_5: # %cmpxchg.nostore
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; CHECK-32-NEXT: #
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; CHECK-32-NEXT: crxor 20, 20, 20
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; CHECK-32-NEXT: b .LBB0_4
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; CHECK-32-NEXT: .LBB0_6: # %atomicrmw.end
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; CHECK-32-NEXT: fmr 1, 0
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; CHECK-32-NEXT: lwsync
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; CHECK-32-NEXT: addi 1, 1, 32
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; CHECK-32-NEXT: blr
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entry:
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%r = atomicrmw fadd ptr %ptr, float %incr seq_cst
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ret float %r
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}
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