e1aef5ed5f
NF (No-Flags) instructions should not compress to non-NF instructions, as this would incorrectly modify flags behavior. The compression table is only intended for encoding optimizations that preserve semantics. This removes the incorrect NF entries that could have led to miscompilation if the compression logic were applied.
383 lines
13 KiB
C++
383 lines
13 KiB
C++
//========- utils/TableGen/X86InstrMappingEmitter.cpp - X86 backend-*- C++ -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This tablegen backend is responsible for emitting the X86 backend
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/// instruction mapping.
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///
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//===----------------------------------------------------------------------===//
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#include "Common/CodeGenInstruction.h"
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#include "Common/CodeGenTarget.h"
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#include "X86RecognizableInstr.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <map>
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#include <set>
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using namespace llvm;
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using namespace X86Disassembler;
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namespace {
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class X86InstrMappingEmitter {
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const RecordKeeper &Records;
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const CodeGenTarget Target;
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// Hold all pontentially compressible EVEX instructions
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std::vector<const CodeGenInstruction *> PreCompressionInsts;
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// Hold all compressed instructions. Divided into groups with same opcodes
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// to make the search more efficient
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std::map<uint64_t, std::vector<const CodeGenInstruction *>> CompressedInsts;
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using Entry =
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std::pair<const CodeGenInstruction *, const CodeGenInstruction *>;
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using PredicateInstMap =
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std::map<StringRef, std::vector<const CodeGenInstruction *>>;
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// Hold all compressed instructions that need to check predicate
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PredicateInstMap PredicateInsts;
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public:
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X86InstrMappingEmitter(const RecordKeeper &R) : Records(R), Target(R) {}
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// run - Output X86 EVEX compression tables.
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void run(raw_ostream &OS);
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private:
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void emitCompressEVEXTable(ArrayRef<const CodeGenInstruction *> Insts,
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raw_ostream &OS);
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void emitNFTransformTable(ArrayRef<const CodeGenInstruction *> Insts,
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raw_ostream &OS);
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void emitND2NonNDTable(ArrayRef<const CodeGenInstruction *> Insts,
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raw_ostream &OS);
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void emitSSE2AVXTable(ArrayRef<const CodeGenInstruction *> Insts,
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raw_ostream &OS);
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// Prints the definition of class X86TableEntry.
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void printClassDef(raw_ostream &OS);
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// Prints the given table as a C++ array of type X86TableEntry under the guard
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// \p Macro.
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void printTable(ArrayRef<Entry> Table, StringRef Name, StringRef Macro,
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raw_ostream &OS);
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};
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} // namespace
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void X86InstrMappingEmitter::printClassDef(raw_ostream &OS) {
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OS << "struct X86TableEntry {\n"
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" uint16_t OldOpc;\n"
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" uint16_t NewOpc;\n"
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" bool operator<(const X86TableEntry &RHS) const {\n"
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" return OldOpc < RHS.OldOpc;\n"
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" }"
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" friend bool operator<(const X86TableEntry &TE, unsigned Opc) {\n"
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" return TE.OldOpc < Opc;\n"
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" }\n"
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"};";
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OS << "\n\n";
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}
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static void printMacroBegin(StringRef Macro, raw_ostream &OS) {
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OS << "\n#ifdef " << Macro << "\n";
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}
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static void printMacroEnd(StringRef Macro, raw_ostream &OS) {
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OS << "#endif // " << Macro << "\n\n";
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}
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void X86InstrMappingEmitter::printTable(ArrayRef<Entry> Table, StringRef Name,
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StringRef Macro, raw_ostream &OS) {
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printMacroBegin(Macro, OS);
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OS << "static const X86TableEntry " << Name << "[] = {\n";
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// Print all entries added to the table
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for (const auto &Pair : Table)
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OS << " { X86::" << Pair.first->getName()
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<< ", X86::" << Pair.second->getName() << " },\n";
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OS << "};\n\n";
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printMacroEnd(Macro, OS);
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}
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namespace {
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class IsMatch {
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const CodeGenInstruction *OldInst;
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public:
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IsMatch(const CodeGenInstruction *OldInst) : OldInst(OldInst) {}
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bool operator()(const CodeGenInstruction *NewInst) {
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RecognizableInstrBase NewRI(*NewInst);
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RecognizableInstrBase OldRI(*OldInst);
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// Return false if any of the following fields of does not match.
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if (std::tuple(OldRI.IsCodeGenOnly, OldRI.OpMap, NewRI.OpPrefix,
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OldRI.HasVEX_4V, OldRI.HasVEX_L, OldRI.HasREX_W,
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OldRI.Form) !=
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std::tuple(NewRI.IsCodeGenOnly, NewRI.OpMap, OldRI.OpPrefix,
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NewRI.HasVEX_4V, NewRI.HasVEX_L, NewRI.HasREX_W, NewRI.Form))
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return false;
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for (unsigned I = 0, E = OldInst->Operands.size(); I < E; ++I) {
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const Record *OldOpRec = OldInst->Operands[I].Rec;
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const Record *NewOpRec = NewInst->Operands[I].Rec;
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if (OldOpRec == NewOpRec)
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continue;
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if (isRegisterOperand(OldOpRec) && isRegisterOperand(NewOpRec)) {
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if (getRegOperandSize(OldOpRec) != getRegOperandSize(NewOpRec))
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return false;
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} else if (isMemoryOperand(OldOpRec) && isMemoryOperand(NewOpRec)) {
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if (getMemOperandSize(OldOpRec) != getMemOperandSize(NewOpRec))
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return false;
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} else if (isImmediateOperand(OldOpRec) && isImmediateOperand(NewOpRec)) {
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if (OldOpRec->getValueAsDef("Type") != NewOpRec->getValueAsDef("Type"))
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return false;
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}
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}
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return true;
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}
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};
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} // namespace
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static bool isInteresting(const Record *Rec) {
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// _REV instruction should not appear before encoding optimization
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return Rec->isSubClassOf("X86Inst") &&
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!Rec->getValueAsBit("isAsmParserOnly") &&
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!Rec->getName().ends_with("_REV");
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}
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void X86InstrMappingEmitter::emitCompressEVEXTable(
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ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
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const std::map<StringRef, StringRef> ManualMap = {
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#define ENTRY(OLD, NEW) {#OLD, #NEW},
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#include "X86ManualInstrMapping.def"
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};
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const std::set<StringRef> NoCompressSet = {
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#define NOCOMP(INSN) #INSN,
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#include "X86ManualInstrMapping.def"
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};
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for (const CodeGenInstruction *Inst : Insts) {
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const Record *Rec = Inst->TheDef;
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StringRef Name = Rec->getName();
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if (!isInteresting(Rec))
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continue;
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// Promoted legacy instruction is in EVEX space, and has REX2-encoding
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// alternative. It's added due to HW design and never emitted by compiler.
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if (byteFromBitsInit(Rec->getValueAsBitsInit("OpMapBits")) ==
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X86Local::T_MAP4 &&
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byteFromBitsInit(Rec->getValueAsBitsInit("explicitOpPrefixBits")) ==
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X86Local::ExplicitEVEX)
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continue;
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if (NoCompressSet.find(Name) != NoCompressSet.end())
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continue;
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RecognizableInstrBase RI(*Inst);
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bool IsND = RI.OpMap == X86Local::T_MAP4 && RI.HasEVEX_B && RI.HasVEX_4V;
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bool IsSETZUCCm = Name == "SETZUCCm";
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// Add VEX encoded instructions to one of CompressedInsts vectors according
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// to it's opcode.
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if (RI.Encoding == X86Local::VEX)
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CompressedInsts[RI.Opcode].push_back(Inst);
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// Add relevant EVEX encoded instructions to PreCompressionInsts.
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// Exclude instructions with:
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// - EVEX_K (mask register)
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// - EVEX_L2 (512-bit vectors)
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// - EVEX_NF (No Flags) - VEX/legacy encodings don't support NF
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// - EVEX_B (broadcast/rounding) unless it's NDD or SETZUCCm
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else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 &&
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!RI.HasEVEX_NF && (!RI.HasEVEX_B || IsND || IsSETZUCCm))
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PreCompressionInsts.push_back(Inst);
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}
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std::vector<Entry> Table;
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for (const CodeGenInstruction *Inst : PreCompressionInsts) {
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const Record *Rec = Inst->TheDef;
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uint8_t Opcode = byteFromBitsInit(Rec->getValueAsBitsInit("Opcode"));
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StringRef Name = Rec->getName();
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const CodeGenInstruction *NewInst = nullptr;
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if (ManualMap.find(Name) != ManualMap.end()) {
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const Record *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
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assert(NewRec && "Instruction not found!");
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NewInst = &Target.getInstruction(NewRec);
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} else if (Name.ends_with("_EVEX")) {
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if (const auto *NewRec = Records.getDef(Name.drop_back(5)))
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NewInst = &Target.getInstruction(NewRec);
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} else if (Name.ends_with("_ND"))
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// Leave it to ND2NONND table.
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continue;
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else {
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// For each pre-compression instruction look for a match in the
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// appropriate vector (instructions with the same opcode) using function
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// object IsMatch.
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const auto &Insts = CompressedInsts[Opcode];
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auto Match = llvm::find_if(Insts, IsMatch(Inst));
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if (Match != Insts.end())
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NewInst = *Match;
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}
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if (!NewInst)
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continue;
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Table.emplace_back(Inst, NewInst);
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auto Predicates = NewInst->TheDef->getValueAsListOfDefs("Predicates");
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auto It = llvm::find_if(Predicates, [](const Record *R) {
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StringRef Name = R->getName();
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return Name == "HasAVXNECONVERT" || Name == "HasAVXVNNI" ||
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Name == "HasAVXIFMA" || Name == "HasAVXVNNIINT8" ||
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Name == "HasAVXVNNIINT16";
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});
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if (It != Predicates.end())
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PredicateInsts[(*It)->getValueAsString("CondString")].push_back(NewInst);
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}
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StringRef Macro = "GET_X86_COMPRESS_EVEX_TABLE";
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printTable(Table, "X86CompressEVEXTable", Macro, OS);
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// Prints function which checks target feature for compressed instructions.
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printMacroBegin(Macro, OS);
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OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget "
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"*Subtarget) {\n"
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<< " switch (Opc) {\n"
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<< " default: return true;\n";
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for (const auto &[Key, Val] : PredicateInsts) {
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for (const auto &Inst : Val)
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OS << " case X86::" << Inst->getName() << ":\n";
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OS << " return " << Key << ";\n";
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}
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OS << " }\n";
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OS << "}\n\n";
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printMacroEnd(Macro, OS);
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}
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void X86InstrMappingEmitter::emitNFTransformTable(
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ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
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std::vector<Entry> Table;
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for (const CodeGenInstruction *Inst : Insts) {
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const Record *Rec = Inst->TheDef;
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if (!isInteresting(Rec))
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continue;
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StringRef Name = Rec->getName();
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if (Name.contains("_NF"))
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continue;
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if (auto *NewRec = Name.consume_back("_ND")
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? Records.getDef(Name.str() + "_NF_ND")
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: Records.getDef(Name.str() + "_NF")) {
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#ifndef NDEBUG
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auto ClobberEFLAGS = [](const Record *R) {
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return llvm::any_of(
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R->getValueAsListOfDefs("Defs"),
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[](const Record *Def) { return Def->getName() == "EFLAGS"; });
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};
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if (ClobberEFLAGS(NewRec))
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report_fatal_error("EFLAGS should not be clobbered by " +
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NewRec->getName());
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if (!ClobberEFLAGS(Rec))
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report_fatal_error("EFLAGS should be clobbered by " + Rec->getName());
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#endif
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Table.emplace_back(Inst, &Target.getInstruction(NewRec));
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}
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}
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printTable(Table, "X86NFTransformTable", "GET_X86_NF_TRANSFORM_TABLE", OS);
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}
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void X86InstrMappingEmitter::emitND2NonNDTable(
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ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
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const std::map<StringRef, StringRef> ManualMap = {
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#define ENTRY_ND(OLD, NEW) {#OLD, #NEW},
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#include "X86ManualInstrMapping.def"
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};
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const std::set<StringRef> NoCompressSet = {
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#define NOCOMP_ND(INSN) #INSN,
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#include "X86ManualInstrMapping.def"
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};
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std::vector<Entry> Table;
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for (const CodeGenInstruction *Inst : Insts) {
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const Record *Rec = Inst->TheDef;
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StringRef Name = Rec->getName();
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if (!isInteresting(Rec) || NoCompressSet.find(Name) != NoCompressSet.end())
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continue;
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if (ManualMap.find(Name) != ManualMap.end()) {
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const auto *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
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assert(NewRec && "Instruction not found!");
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auto &NewInst = Target.getInstruction(NewRec);
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Table.emplace_back(Inst, &NewInst);
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continue;
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}
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if (!Name.ends_with("_ND"))
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continue;
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const auto *NewRec = Records.getDef(Name.drop_back(3));
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if (!NewRec)
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continue;
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const auto &NewInst = Target.getInstruction(NewRec);
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if (isRegisterOperand(NewInst.Operands[0].Rec))
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Table.emplace_back(Inst, &NewInst);
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}
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printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
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}
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void X86InstrMappingEmitter::emitSSE2AVXTable(
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ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
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const std::map<StringRef, StringRef> ManualMap = {
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#define ENTRY_SSE2AVX(OLD, NEW) {#OLD, #NEW},
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#include "X86ManualInstrMapping.def"
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};
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std::vector<Entry> Table;
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for (const CodeGenInstruction *Inst : Insts) {
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const Record *Rec = Inst->TheDef;
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StringRef Name = Rec->getName();
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if (!isInteresting(Rec))
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continue;
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if (ManualMap.find(Name) != ManualMap.end()) {
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const auto *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
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assert(NewRec && "Instruction not found!");
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const auto &NewInst = Target.getInstruction(NewRec);
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Table.emplace_back(Inst, &NewInst);
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continue;
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}
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std::string NewName = ("V" + Name).str();
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const auto *AVXRec = Records.getDef(NewName);
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if (!AVXRec)
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continue;
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auto &AVXInst = Target.getInstruction(AVXRec);
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Table.emplace_back(Inst, &AVXInst);
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}
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printTable(Table, "X86SSE2AVXTable", "GET_X86_SSE2AVX_TABLE", OS);
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}
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void X86InstrMappingEmitter::run(raw_ostream &OS) {
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emitSourceFileHeader("X86 instruction mapping", OS);
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ArrayRef<const CodeGenInstruction *> Insts = Target.getInstructions();
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printClassDef(OS);
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emitCompressEVEXTable(Insts, OS);
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emitNFTransformTable(Insts, OS);
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emitND2NonNDTable(Insts, OS);
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emitSSE2AVXTable(Insts, OS);
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}
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static TableGen::Emitter::OptClass<X86InstrMappingEmitter>
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X("gen-x86-instr-mapping", "Generate X86 instruction mapping");
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