3459bb4f27
This is useful for `InstAlias` where a fixed register may depend on the
HwMode. The motivating use case for this is the RISC-V RVY ISA where
certain instructions mnemonics are remapped to take a different
register class depending on the HwMode and can be used as follows:
```
def NullReg : RegisterByHwMode<PtrRC, [RV32I, RV64I, RV64Y, RV64Y],
[X0, X0, X0_Y, X0_Y]>;
```
Pull Request: https://github.com/llvm/llvm-project/pull/175227
282 lines
10 KiB
C++
282 lines
10 KiB
C++
//===--- InfoByHwMode.cpp -------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Classes that implement data parameterized by HW modes for instruction
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// selection. Currently it is ValueTypeByHwMode (parameterized ValueType),
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// and RegSizeInfoByHwMode (parameterized register/spill size and alignment
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// data).
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//===----------------------------------------------------------------------===//
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#include "InfoByHwMode.h"
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#include "CodeGenRegisters.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include <string>
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using namespace llvm;
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std::string llvm::getModeName(unsigned Mode) {
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if (Mode == DefaultMode)
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return "*";
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return (Twine('m') + Twine(Mode)).str();
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}
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ValueTypeByHwMode::ValueTypeByHwMode(const Record *R, const CodeGenHwModes &CGH)
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: InfoByHwMode<llvm::MVT>(R) {
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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for (auto [ModeID, VT] : MS.Items) {
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assert(VT && VT->isSubClassOf("ValueType"));
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if (!Map.try_emplace(ModeID, MVT(llvm::getValueType(VT))).second)
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PrintFatalError(R->getLoc(), "duplicate ValueType entry for HwMode " +
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CGH.getModeName(ModeID, true) + ": " +
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VT->getName());
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}
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if (R->isSubClassOf("PtrValueType"))
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PtrAddrSpace = R->getValueAsInt("AddrSpace");
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}
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ValueTypeByHwMode::ValueTypeByHwMode(const Record *R, MVT T)
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: ValueTypeByHwMode(T) {
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if (R->isSubClassOf("PtrValueType"))
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PtrAddrSpace = R->getValueAsInt("AddrSpace");
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}
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bool ValueTypeByHwMode::operator==(const ValueTypeByHwMode &T) const {
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assert(isValid() && T.isValid() && "Invalid type in assignment");
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bool Simple = isSimple();
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if (Simple != T.isSimple())
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return false;
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if (Simple)
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return getSimple() == T.getSimple();
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return Map == T.Map;
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}
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bool ValueTypeByHwMode::operator<(const ValueTypeByHwMode &T) const {
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assert(isValid() && T.isValid() && "Invalid type in comparison");
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// Default order for maps.
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return Map < T.Map;
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}
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StringRef ValueTypeByHwMode::getMVTName(MVT T) {
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StringRef N = llvm::getEnumName(T.SimpleTy);
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N.consume_front("MVT::");
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return N;
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}
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void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
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if (isSimple()) {
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OS << getMVTName(getSimple());
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return;
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}
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std::vector<const PairType *> Pairs;
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for (const auto &P : Map)
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Pairs.push_back(&P);
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llvm::sort(Pairs, deref<std::less<PairType>>());
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OS << '{';
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ListSeparator LS(",");
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for (const PairType *P : Pairs)
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OS << LS << '(' << getModeName(P->first) << ':'
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<< getMVTName(P->second).str() << ')';
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OS << '}';
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}
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LLVM_DUMP_METHOD
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void ValueTypeByHwMode::dump() const { dbgs() << *this << '\n'; }
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ValueTypeByHwMode llvm::getValueTypeByHwMode(const Record *Rec,
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const CodeGenHwModes &CGH) {
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#ifndef NDEBUG
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if (!Rec->isSubClassOf("ValueType"))
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Rec->dump();
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#endif
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assert(Rec->isSubClassOf("ValueType") &&
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"Record must be derived from ValueType");
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if (Rec->isSubClassOf("HwModeSelect"))
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return ValueTypeByHwMode(Rec, CGH);
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return ValueTypeByHwMode(Rec, llvm::getValueType(Rec));
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}
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RegSizeInfo::RegSizeInfo(const Record *R) {
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RegSize = R->getValueAsInt("RegSize");
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SpillSize = R->getValueAsInt("SpillSize");
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SpillAlignment = R->getValueAsInt("SpillAlignment");
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}
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bool RegSizeInfo::operator<(const RegSizeInfo &I) const {
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return std::tie(RegSize, SpillSize, SpillAlignment) <
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std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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}
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bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const {
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return RegSize <= I.RegSize && SpillAlignment &&
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I.SpillAlignment % SpillAlignment == 0 && SpillSize <= I.SpillSize;
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}
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void RegSizeInfo::writeToStream(raw_ostream &OS) const {
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OS << "[R=" << RegSize << ",S=" << SpillSize << ",A=" << SpillAlignment
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<< ']';
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}
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RegSizeInfoByHwMode::RegSizeInfoByHwMode(const Record *R,
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const CodeGenHwModes &CGH)
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: InfoByHwMode<llvm::RegSizeInfo>(R) {
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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for (auto [ModeID, RegInfo] : MS.Items) {
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assert(RegInfo && RegInfo->isSubClassOf("RegInfo"));
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if (!Map.try_emplace(ModeID, RegSizeInfo(RegInfo)).second)
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PrintFatalError(R->getLoc(), "duplicate RegInfo entry for HwMode " +
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CGH.getModeName(ModeID, true) + ": " +
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RegInfo->getName());
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}
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}
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bool RegSizeInfoByHwMode::operator<(const RegSizeInfoByHwMode &I) const {
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unsigned M0 = Map.begin()->first;
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return get(M0) < I.get(M0);
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}
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bool RegSizeInfoByHwMode::operator==(const RegSizeInfoByHwMode &I) const {
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unsigned M0 = Map.begin()->first;
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return get(M0) == I.get(M0);
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}
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bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const {
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unsigned M0 = Map.begin()->first;
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return get(M0).isSubClassOf(I.get(M0));
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}
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bool RegSizeInfoByHwMode::hasStricterSpillThan(
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const RegSizeInfoByHwMode &I) const {
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unsigned M0 = Map.begin()->first;
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const RegSizeInfo &A0 = get(M0);
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const RegSizeInfo &B0 = I.get(M0);
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return std::tie(A0.SpillSize, A0.SpillAlignment) >
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std::tie(B0.SpillSize, B0.SpillAlignment);
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}
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void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
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using PairType = decltype(Map)::value_type;
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std::vector<const PairType *> Pairs;
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for (const auto &P : Map)
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Pairs.push_back(&P);
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llvm::sort(Pairs, deref<std::less<PairType>>());
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OS << '{';
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ListSeparator LS(",");
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for (const PairType *P : Pairs)
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OS << LS << '(' << getModeName(P->first) << ':' << P->second << ')';
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OS << '}';
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}
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RegClassByHwMode::RegClassByHwMode(const Record *R,
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const CodeGenRegBank &RegBank)
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: InfoByHwMode<const llvm::CodeGenRegisterClass *>(R) {
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const CodeGenHwModes &CGH = RegBank.getHwModes();
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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for (auto [ModeID, RegClassRec] : MS.Items) {
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assert(RegClassRec && RegClassRec->isSubClassOf("RegisterClass") &&
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"Register class must subclass RegisterClass");
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const CodeGenRegisterClass *RegClass = RegBank.getRegClass(RegClassRec);
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if (!Map.try_emplace(ModeID, RegClass).second)
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PrintFatalError(R->getLoc(), "duplicate RegisterClass entry for HwMode " +
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CGH.getModeName(ModeID, true) + ": " +
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RegClass->getName());
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}
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}
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SubRegRange::SubRegRange(const Record *R) {
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Size = R->getValueAsInt("Size");
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Offset = R->getValueAsInt("Offset");
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}
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SubRegRangeByHwMode::SubRegRangeByHwMode(const Record *R,
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const CodeGenHwModes &CGH)
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: InfoByHwMode<llvm::SubRegRange>(R) {
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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for (auto [ModeID, Range] : MS.Items) {
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assert(Range && Range->isSubClassOf("SubRegRange"));
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if (!Map.try_emplace(ModeID, SubRegRange(Range)).second)
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PrintFatalError(R->getLoc(), "duplicate SubRegRange entry for HwMode " +
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CGH.getModeName(ModeID, true) + ": " +
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Range->getName());
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}
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}
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EncodingInfoByHwMode::EncodingInfoByHwMode(const Record *R,
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const CodeGenHwModes &CGH)
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: InfoByHwMode<const llvm::Record *>(R) {
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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for (auto [ModeID, Encoding] : MS.Items) {
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assert(Encoding && Encoding->isSubClassOf("InstructionEncoding") &&
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"Encoding must subclass InstructionEncoding");
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if (!Map.try_emplace(ModeID, Encoding).second)
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PrintFatalError(R->getLoc(),
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"duplicate InstructionEncoding entry for HwMode " +
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CGH.getModeName(ModeID, true) + ": " +
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Encoding->getName());
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}
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}
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RegisterByHwMode::RegisterByHwMode(const Record *R, CodeGenRegBank &RegBank)
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: InfoByHwMode<const llvm::CodeGenRegister *>(R) {
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const CodeGenHwModes &CGH = RegBank.getHwModes();
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const HwModeSelect &MS = CGH.getHwModeSelect(R);
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const Record *RCDef = R->getValueAsDef("RegClass");
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Namespace = RegBank.getRegClasses().front().Namespace;
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std::optional<RegClassByHwMode> RegClassByMode;
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if (RCDef->isSubClassOf("RegClassByHwMode"))
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RegClassByMode = RegClassByHwMode(RCDef, RegBank);
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for (auto [ModeID, RegRecord] : MS.Items) {
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assert(RegRecord && RegRecord->isSubClassOf("Register") &&
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"Register value must subclass Register");
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CodeGenRegister *Reg = RegBank.getReg(RegRecord);
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const CodeGenRegisterClass *RC =
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RegClassByMode ? RegClassByMode->get(ModeID)
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: RegBank.getRegClass(RCDef, R->getLoc());
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if (!RC->contains(Reg))
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PrintFatalError(R->getLoc(), "Register " + Reg->getName() +
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" for HwMode " +
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CGH.getModeName(ModeID, true) +
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" is not a member of register class " +
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RC->getName());
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if (!Map.try_emplace(ModeID, Reg).second)
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PrintFatalError(R->getLoc(), "duplicate Register for HwMode " +
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CGH.getModeName(ModeID, true) + ": " +
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Reg->getName());
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}
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}
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void RegisterByHwMode::emitResolverCall(raw_ostream &OS,
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const Twine &HwMode) const {
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OS << Namespace << "::RegisterByHwMode::get" << Def->getName() << "("
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<< HwMode << ")";
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}
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raw_ostream &llvm::operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
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T.writeToStream(OS);
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return OS;
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}
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raw_ostream &llvm::operator<<(raw_ostream &OS, const RegSizeInfo &T) {
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T.writeToStream(OS);
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return OS;
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}
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raw_ostream &llvm::operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
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T.writeToStream(OS);
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return OS;
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}
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