cac7fe50e0
The canonical IV is directly tied to a loop region. To directly ensure there's a single, unique canonical IV, directly define it by the region. Depends on https://github.com/llvm/llvm-project/pull/161589. PR: https://github.com/llvm/llvm-project/pull/156262
490 lines
17 KiB
C++
490 lines
17 KiB
C++
//===- llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../lib/Transforms/Vectorize/VPlanVerifier.h"
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#include "../lib/Transforms/Vectorize/VPlan.h"
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#include "../lib/Transforms/Vectorize/VPlanCFG.h"
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#include "VPlanTestBase.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace llvm {
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LLVM_ABI extern cl::opt<bool> VerifyEachVPlan;
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} // namespace llvm
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using VPVerifierTest = VPlanTestBase;
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namespace {
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TEST_F(VPVerifierTest, VPInstructionUseBeforeDefSameBB) {
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VPlan &Plan = getPlan();
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VPIRValue *Zero = Plan.getConstantInt(32, 0);
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VPInstruction *DefI =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPInstruction *UseI =
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new VPInstruction(Instruction::Sub, {DefI, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Sub));
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBB1->appendRecipe(UseI);
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VPBB1->appendRecipe(DefI);
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("");
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// Add a dummy instruction to VPBB2 to make it non-empty
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VPInstruction *Dummy =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPBB2->appendRecipe(Dummy);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB2, VPBB2);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBlockUtils::connectBlocks(R1, Plan.getScalarHeader());
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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EXPECT_STREQ("Use before def!\n"
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" EMIT vp<%1> = sub vp<%2>, ir<0>\n"
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" before\n"
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" EMIT vp<%2> = add ir<0>, ir<0>\n",
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::testing::internal::GetCapturedStderr().c_str());
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#else
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EXPECT_STREQ("Use before def!\n",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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#endif
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}
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TEST_F(VPVerifierTest, VPInstructionUseBeforeDefDifferentBB) {
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VPlan &Plan = getPlan();
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VPIRValue *Zero = Plan.getConstantInt(32, 0);
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VPInstruction *DefI =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPInstruction *UseI =
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new VPInstruction(Instruction::Sub, {DefI, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Sub));
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VPInstruction *BranchOnCond =
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new VPInstruction(VPInstruction::BranchOnCond, {UseI});
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("");
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VPBB1->appendRecipe(UseI);
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VPBB2->appendRecipe(DefI);
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VPBB2->appendRecipe(BranchOnCond);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB2, VPBB2);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBlockUtils::connectBlocks(R1, Plan.getScalarHeader());
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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EXPECT_STREQ("Use before def!\n"
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" EMIT vp<%1> = sub vp<%3>, ir<0>\n"
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" before\n"
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" EMIT vp<%3> = add ir<0>, ir<0>\n",
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::testing::internal::GetCapturedStderr().c_str());
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#else
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EXPECT_STREQ("Use before def!\n",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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#endif
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}
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TEST_F(VPVerifierTest, VPBlendUseBeforeDefDifferentBB) {
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VPlan &Plan = getPlan();
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IntegerType *Int32 = IntegerType::get(C, 32);
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auto *Phi = PHINode::Create(Int32, 1);
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VPIRValue *Zero = Plan.getConstantInt(Int32, 0);
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VPInstruction *DefI =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPInstruction *BranchOnCond =
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new VPInstruction(VPInstruction::BranchOnCond, {DefI});
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auto *Blend = new VPBlendRecipe(Phi, {DefI, Plan.getTrue()}, {}, {});
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("");
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VPBasicBlock *VPBB3 = Plan.createVPBasicBlock("");
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VPBasicBlock *VPBB4 = Plan.createVPBasicBlock("");
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VPBB3->appendRecipe(Blend);
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VPBB4->appendRecipe(DefI);
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VPBB4->appendRecipe(BranchOnCond);
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VPBlockUtils::connectBlocks(VPBB2, VPBB3);
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VPBlockUtils::connectBlocks(VPBB3, VPBB4);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB2, VPBB4);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBB3->setParent(R1);
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VPBlockUtils::connectBlocks(R1, Plan.getScalarHeader());
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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EXPECT_STREQ("Use before def!\n"
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" BLEND ir<<badref>> = vp<%2>\n"
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" before\n"
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" EMIT vp<%2> = add ir<0>, ir<0>\n",
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::testing::internal::GetCapturedStderr().c_str());
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#else
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EXPECT_STREQ("Use before def!\n",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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#endif
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delete Phi;
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}
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TEST_F(VPVerifierTest, VPPhiIncomingValueDoesntDominateIncomingBlock) {
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VPlan &Plan = getPlan();
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IntegerType *Int32 = IntegerType::get(C, 32);
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VPIRValue *Zero = Plan.getConstantInt(Int32, 0);
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("");
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VPBasicBlock *VPBB3 = Plan.createVPBasicBlock("");
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VPBasicBlock *VPBB4 = Plan.createVPBasicBlock("");
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VPInstruction *DefI =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPPhi *Phi = new VPPhi({DefI}, {}, {});
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VPBB2->appendRecipe(Phi);
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VPBB2->appendRecipe(DefI);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB3, VPBB3);
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VPBlockUtils::connectBlocks(VPBB1, VPBB2);
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VPBlockUtils::connectBlocks(VPBB2, R1);
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VPBlockUtils::connectBlocks(VPBB4, Plan.getScalarHeader());
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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EXPECT_STREQ("Incoming def does not dominate incoming block!\n"
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" EMIT vp<%2> = add ir<0>, ir<0>\n"
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" does not dominate preheader for\n"
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" EMIT-SCALAR vp<%1> = phi [ vp<%2>, preheader ]",
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::testing::internal::GetCapturedStderr().c_str());
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#else
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EXPECT_STREQ("Incoming def does not dominate incoming block!\n",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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#endif
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}
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TEST_F(VPVerifierTest, DuplicateSuccessorsOutsideRegion) {
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VPlan &Plan = getPlan();
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VPIRValue *Zero = Plan.getConstantInt(32, 0);
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VPInstruction *I1 =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPInstruction *BranchOnCond =
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new VPInstruction(VPInstruction::BranchOnCond, {I1});
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VPInstruction *BranchOnCond2 =
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new VPInstruction(VPInstruction::BranchOnCond, {I1});
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("");
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VPBB1->appendRecipe(I1);
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VPBB1->appendRecipe(BranchOnCond2);
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VPBB2->appendRecipe(BranchOnCond);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB2, VPBB2);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBlockUtils::connectBlocks(R1, Plan.getScalarHeader());
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// Duplicate successors are allowed for blocks with conditional terminators.
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EXPECT_TRUE(verifyVPlanIsValid(Plan));
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}
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TEST_F(VPVerifierTest, DuplicateSuccessorsInsideRegion) {
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VPlan &Plan = getPlan();
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VPIRValue *Zero = Plan.getConstantInt(32, 0);
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VPInstruction *I1 =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPInstruction *BranchOnCond =
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new VPInstruction(VPInstruction::BranchOnCond, {I1});
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VPInstruction *BranchOnCond2 =
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new VPInstruction(VPInstruction::BranchOnCond, {I1});
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("");
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VPBasicBlock *VPBB3 = Plan.createVPBasicBlock("");
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VPBB1->appendRecipe(I1);
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VPBB2->appendRecipe(BranchOnCond2);
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VPBB3->appendRecipe(BranchOnCond);
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VPBlockUtils::connectBlocks(VPBB2, VPBB3);
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VPBlockUtils::connectBlocks(VPBB2, VPBB3);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB2, VPBB3);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBB3->setParent(R1);
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VPBlockUtils::connectBlocks(R1, Plan.getScalarHeader());
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// Duplicate successors are allowed for blocks with conditional terminators.
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EXPECT_TRUE(verifyVPlanIsValid(Plan));
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}
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TEST_F(VPVerifierTest, BlockOutsideRegionWithParent) {
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VPlan &Plan = getPlan();
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("");
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VPValue *Zero = Plan.getConstantInt(32, 0);
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VPInstruction *DefI =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPInstruction *BranchOnCond =
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new VPInstruction(VPInstruction::BranchOnCond, {DefI});
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VPBB1->appendRecipe(DefI);
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VPBB2->appendRecipe(BranchOnCond);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB2, VPBB2);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBlockUtils::connectBlocks(R1, Plan.getScalarHeader());
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VPBB1->setParent(R1);
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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EXPECT_STREQ("Predecessor is not in the same region.\n",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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}
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TEST_F(VPVerifierTest, NonHeaderPHIInHeader) {
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VPlan &Plan = getPlan();
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VPValue *Zero = Plan.getConstantInt(32, 0);
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auto *BranchOnCond = new VPInstruction(VPInstruction::BranchOnCond, {Zero});
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBasicBlock *VPBB2 = Plan.createVPBasicBlock("header");
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PHINode *PHINode = PHINode::Create(Type::getInt32Ty(C), 2);
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auto *IRPhi = new VPIRPhi(*PHINode);
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VPBB2->appendRecipe(IRPhi);
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VPBB2->appendRecipe(BranchOnCond);
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VPRegionBlock *R1 = Plan.createLoopRegion(Type::getInt32Ty(C), DebugLoc(),
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"R1", VPBB2, VPBB2);
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VPBlockUtils::connectBlocks(VPBB1, R1);
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VPBlockUtils::connectBlocks(R1, Plan.getScalarHeader());
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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EXPECT_STREQ(
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"Found non-header PHI recipe in header VPBB: IR <badref> = phi i32 \n",
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::testing::internal::GetCapturedStderr().c_str());
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#else
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EXPECT_STREQ("Found non-header PHI recipe in header VPBB",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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#endif
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delete PHINode;
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}
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TEST_F(VPVerifierTest, testRUN_VPLAN_PASS) {
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VPlan &Plan = getPlan();
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VPIRValue *Zero = Plan.getConstantInt(32, 0);
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VPInstruction *DefI =
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new VPInstruction(Instruction::Add, {Zero, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Add));
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VPInstruction *UseI =
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new VPInstruction(Instruction::Sub, {DefI, Zero},
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VPIRFlags::getDefaultFlags(Instruction::Sub));
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VPBasicBlock *VPBB1 = Plan.getEntry();
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VPBB1->appendRecipe(UseI);
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VPBB1->appendRecipe(DefI);
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bool OrigVerifyEachVPlan = VerifyEachVPlan;
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VerifyEachVPlan = true;
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llvm::scope_exit _([&]() { VerifyEachVPlan = OrigVerifyEachVPlan; });
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auto NopPass = [](VPlan &Plan) {};
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EXPECT_DEATH(
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{ VPlanTransforms::runPass("simplifyRecipes", NopPass, Plan); },
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"Broken VPlan found, compilation aborted!");
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}
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class VPIRVerifierTest : public VPlanTestIRBase {};
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TEST_F(VPIRVerifierTest, testVerifyIRPhiInScalarHeaderVPIRBB) {
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const char *ModuleString =
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"define void @f(ptr %A, i64 %N) {\n"
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"entry:\n"
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" br label %loop\n"
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"loop:\n"
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" %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]\n"
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" %iv.next = add i64 %iv, 1\n"
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" %exitcond = icmp ne i64 %iv.next, %N\n"
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" br i1 %exitcond, label %loop, label %for.end\n"
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"for.end:\n"
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" %p = phi i64 [ %iv, %loop ]\n"
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" ret void\n"
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"}\n";
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Module &M = parseModule(ModuleString);
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Function *F = M.getFunction("f");
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BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
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auto Plan = buildVPlan(LoopHeader);
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VPValue *Zero = Plan->getConstantInt(32, 0);
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Plan->getScalarHeader()->front().addOperand(Zero);
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(*Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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EXPECT_STREQ(
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"Phi-like recipe with different number of operands and predecessors.\n",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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}
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TEST_F(VPIRVerifierTest, testVerifyIRPhiInExitVPIRBB) {
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const char *ModuleString =
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"define void @f(ptr %A, i64 %N) {\n"
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"entry:\n"
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" br label %loop\n"
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"loop:\n"
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" %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]\n"
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" %iv.next = add i64 %iv, 1\n"
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" %exitcond = icmp ne i64 %iv.next, %N\n"
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" br i1 %exitcond, label %loop, label %for.end\n"
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"for.end:\n"
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" %p = phi i64 [ %iv, %loop ]\n"
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" ret void\n"
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"}\n";
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Module &M = parseModule(ModuleString);
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Function *F = M.getFunction("f");
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BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
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auto Plan = buildVPlan(LoopHeader);
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// Create a definition in the vector loop header that will be used by the phi.
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auto *HeaderBlock =
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cast<VPBasicBlock>(Plan->getVectorLoopRegion()->getEntry());
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VPInstruction *DefI =
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new VPInstruction(VPInstruction::ExtractLastLane,
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{HeaderBlock->front().getVPSingleValue()});
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DefI->insertBefore(Plan->getMiddleBlock()->getTerminator());
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Plan->getExitBlocks()[0]->front().addOperand(DefI);
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#if GTEST_HAS_STREAM_REDIRECTION
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::testing::internal::CaptureStderr();
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#endif
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EXPECT_FALSE(verifyVPlanIsValid(*Plan));
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#if GTEST_HAS_STREAM_REDIRECTION
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EXPECT_STREQ(
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"Phi-like recipe with different number of operands and predecessors.\n",
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::testing::internal::GetCapturedStderr().c_str());
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#endif
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}
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TEST_F(VPIRVerifierTest, BranchOnTwoCondsLatchHeaderVerification) {
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const char *ModuleString =
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"define void @f(ptr dereferenceable(40) align 2 %pred) {\n"
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"entry:\n"
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" br label %for.body\n"
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"for.body:\n"
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" %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.inc ]\n"
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" %uncountable.addr = getelementptr inbounds nuw i16, ptr %pred, i64 "
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"%iv\n"
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" %uncountable.val = load i16, ptr %uncountable.addr, align 2\n"
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" %uncountable.cond = icmp sgt i16 %uncountable.val, 500\n"
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" br i1 %uncountable.cond, label %exit, label %for.inc\n"
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"for.inc:\n"
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|
" %iv.next = add nuw nsw i64 %iv, 1\n"
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|
" %countable.cond = icmp eq i64 %iv.next, 20\n"
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|
" br i1 %countable.cond, label %exit, label %for.body\n"
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|
"exit:\n"
|
|
" ret void\n"
|
|
"}\n";
|
|
|
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Module &M = parseModule(ModuleString);
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|
|
|
Function *F = M.getFunction("f");
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|
BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
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|
// Build a plain CFG VPlan with BranchOnTwoConds as the latch terminator
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|
// (3 successors), without wrapping blocks in loop regions.
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|
auto Plan = buildVPlan(LoopHeader, UncountableExitStyle::ReadOnly,
|
|
/*CreateLoopRegions=*/false);
|
|
|
|
auto *MiddleVPBB =
|
|
cast<VPBasicBlock>(Plan->getScalarPreheader()->getPredecessors()[0]);
|
|
auto *Latch = cast<VPBasicBlock>(MiddleVPBB->getSinglePredecessor());
|
|
auto *Header = Latch->getSuccessors().back();
|
|
ASSERT_EQ(Header->getPredecessors()[1], Latch);
|
|
ASSERT_EQ(Latch->getNumSuccessors(), 3u);
|
|
auto *Term = cast<VPInstruction>(&Latch->back());
|
|
EXPECT_EQ(Term->getOpcode(), VPInstruction::BranchOnTwoConds);
|
|
|
|
// Verify the plan is valid; this exercises isLatch with a 3-successor latch.
|
|
EXPECT_TRUE(verifyVPlanIsValid(*Plan));
|
|
|
|
// Swap the latch's first and last successors, placing the header at index 0
|
|
// instead of the last position. isLatch checks the last successor, so the
|
|
// latch is no longer recognized, triggering the header predecessor check.
|
|
auto &Succs = Latch->getSuccessors();
|
|
std::swap(Succs[0], Succs[2]);
|
|
|
|
#if GTEST_HAS_STREAM_REDIRECTION
|
|
::testing::internal::CaptureStderr();
|
|
#endif
|
|
EXPECT_FALSE(verifyVPlanIsValid(*Plan));
|
|
#if GTEST_HAS_STREAM_REDIRECTION
|
|
EXPECT_STREQ("Header's second predecessor must be the latch!\n",
|
|
::testing::internal::GetCapturedStderr().c_str());
|
|
#endif
|
|
}
|
|
|
|
} // namespace
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