04591cbc7e
On GPUs `TTI::getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector()` returns the element bit width, not the whole vector size as it does on the CPU. So this patch changes this to a call to `getLoadStoreVecRegBitWidth()`, which depends on the address space, so it also moves the calculation per seed. This patch also adds an AMDGPU lit test directory with a simple test.
23 lines
838 B
LLVM
23 lines
838 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=sandbox-vectorizer -sbvec-passes="seed-collection<load-store-vec>" -mtriple=amdgcn--amdhsa -mcpu=gfx900 %s -S | FileCheck %s
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define void @basic(ptr %ptr0) {
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; CHECK-LABEL: define void @basic(
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; CHECK-SAME: ptr [[PTR0:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[VECIINITL:%.*]] = load <2 x float>, ptr [[PTR0]], align 1, !sandboxvec [[META0:![0-9]+]]
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; CHECK-NEXT: store <2 x float> [[VECIINITL]], ptr [[PTR0]], align 1, !sandboxvec [[META0]]
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; CHECK-NEXT: ret void
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;
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%ptr1 = getelementptr inbounds i8, ptr %ptr0, i64 4
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%ld0 = load float, ptr %ptr0
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%ld1 = load float, ptr %ptr1
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store float %ld0, ptr %ptr0
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store float %ld1, ptr %ptr1
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ret void
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}
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;.
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; CHECK: [[META0]] = distinct !{!"sandboxregion"}
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;.
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