0d67b2edac
exp2 maps to a single v_exp_f32 (quarter rate), while exp and exp10 need additional full-rate costs for the base conversion. Also added cost based on non-afn and denorm mode. This enables SLP vectorization of exp2 on targets with packed f32 ops.
84 lines
4.8 KiB
LLVM
84 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefix=GFX9 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -passes=slp-vectorizer %s | FileCheck -check-prefix=GFX1250 %s
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define amdgpu_kernel void @exp2_combine(ptr addrspace(1) %arg) {
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; GFX9-LABEL: define amdgpu_kernel void @exp2_combine(
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; GFX9-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
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; GFX9-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; GFX9-NEXT: [[IDX:%.*]] = zext i32 [[TID]] to i64
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; GFX9-NEXT: [[PTR0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARG]], i64 [[IDX]]
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; GFX9-NEXT: [[VAL0:%.*]] = load float, ptr addrspace(1) [[PTR0]], align 4
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; GFX9-NEXT: [[EXP0:%.*]] = call float @llvm.exp2.f32(float [[VAL0]])
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; GFX9-NEXT: store float [[EXP0]], ptr addrspace(1) [[PTR0]], align 4
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; GFX9-NEXT: [[IDX1:%.*]] = add nuw nsw i64 [[IDX]], 1
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; GFX9-NEXT: [[PTR1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARG]], i64 [[IDX1]]
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; GFX9-NEXT: [[VAL1:%.*]] = load float, ptr addrspace(1) [[PTR1]], align 4
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; GFX9-NEXT: [[EXP1:%.*]] = call float @llvm.exp2.f32(float [[VAL1]])
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; GFX9-NEXT: store float [[EXP1]], ptr addrspace(1) [[PTR1]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX1250-LABEL: define amdgpu_kernel void @exp2_combine(
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; GFX1250-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
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; GFX1250-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; GFX1250-NEXT: [[IDX:%.*]] = zext i32 [[TID]] to i64
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; GFX1250-NEXT: [[PTR0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARG]], i64 [[IDX]]
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; GFX1250-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[PTR0]], align 4
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; GFX1250-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP1]])
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; GFX1250-NEXT: store <2 x float> [[TMP2]], ptr addrspace(1) [[PTR0]], align 4
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; GFX1250-NEXT: ret void
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;
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%idx = zext i32 %tid to i64
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%ptr0 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %idx
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%val0 = load float, ptr addrspace(1) %ptr0, align 4
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%exp0 = call float @llvm.exp2.f32(float %val0)
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store float %exp0, ptr addrspace(1) %ptr0, align 4
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%idx1 = add nuw nsw i64 %idx, 1
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%ptr1 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %idx1
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%val1 = load float, ptr addrspace(1) %ptr1, align 4
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%exp1 = call float @llvm.exp2.f32(float %val1)
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store float %exp1, ptr addrspace(1) %ptr1, align 4
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ret void
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}
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define amdgpu_kernel void @exp_afn_combine(ptr addrspace(1) %arg) {
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; GFX9-LABEL: define amdgpu_kernel void @exp_afn_combine(
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; GFX9-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; GFX9-NEXT: [[IDX:%.*]] = zext i32 [[TID]] to i64
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; GFX9-NEXT: [[PTR0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARG]], i64 [[IDX]]
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; GFX9-NEXT: [[VAL0:%.*]] = load float, ptr addrspace(1) [[PTR0]], align 4
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; GFX9-NEXT: [[EXP0:%.*]] = call afn float @llvm.exp.f32(float [[VAL0]])
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; GFX9-NEXT: store float [[EXP0]], ptr addrspace(1) [[PTR0]], align 4
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; GFX9-NEXT: [[IDX1:%.*]] = add nuw nsw i64 [[IDX]], 1
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; GFX9-NEXT: [[PTR1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARG]], i64 [[IDX1]]
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; GFX9-NEXT: [[VAL1:%.*]] = load float, ptr addrspace(1) [[PTR1]], align 4
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; GFX9-NEXT: [[EXP1:%.*]] = call afn float @llvm.exp.f32(float [[VAL1]])
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; GFX9-NEXT: store float [[EXP1]], ptr addrspace(1) [[PTR1]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX1250-LABEL: define amdgpu_kernel void @exp_afn_combine(
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; GFX1250-SAME: ptr addrspace(1) [[ARG:%.*]]) #[[ATTR0]] {
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; GFX1250-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; GFX1250-NEXT: [[IDX:%.*]] = zext i32 [[TID]] to i64
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; GFX1250-NEXT: [[PTR0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARG]], i64 [[IDX]]
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; GFX1250-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[PTR0]], align 4
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; GFX1250-NEXT: [[TMP2:%.*]] = call afn <2 x float> @llvm.exp.v2f32(<2 x float> [[TMP1]])
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; GFX1250-NEXT: store <2 x float> [[TMP2]], ptr addrspace(1) [[PTR0]], align 4
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; GFX1250-NEXT: ret void
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;
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%idx = zext i32 %tid to i64
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%ptr0 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %idx
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%val0 = load float, ptr addrspace(1) %ptr0, align 4
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%exp0 = call afn float @llvm.exp.f32(float %val0)
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store float %exp0, ptr addrspace(1) %ptr0, align 4
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%idx1 = add nuw nsw i64 %idx, 1
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%ptr1 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %idx1
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%val1 = load float, ptr addrspace(1) %ptr1, align 4
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%exp1 = call afn float @llvm.exp.f32(float %val1)
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store float %exp1, ptr addrspace(1) %ptr1, align 4
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ret void
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}
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