c23b4fbdbb
Now that #149310 has restricted lifetime intrinsics to only work on allocas, we can also drop the explicit size argument. Instead, the size is implied by the alloca. This removes the ability to only mark a prefix of an alloca alive/dead. We never used that capability, so we should remove the need to handle that possibility everywhere (though many key places, including stack coloring, did not actually respect this).
117 lines
5.2 KiB
LLVM
117 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -O2 -S < %s | FileCheck %s
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define <3 x float> @PR52631(<3 x float> %a, <3 x float> %b, <3 x i32> %c) {
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; CHECK-LABEL: @PR52631(
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; CHECK-NEXT: [[ISNEG3:%.*]] = icmp slt <3 x i32> [[C:%.*]], zeroinitializer
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; CHECK-NEXT: [[OR_V:%.*]] = select <3 x i1> [[ISNEG3]], <3 x float> [[B:%.*]], <3 x float> [[A:%.*]]
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; CHECK-NEXT: ret <3 x float> [[OR_V]]
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;
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%a.addr = alloca <3 x float>, align 16
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%b.addr = alloca <3 x float>, align 16
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%c.addr = alloca <3 x i32>, align 16
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%zero = alloca <3 x i32>, align 16
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%mask = alloca <3 x i32>, align 16
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%res = alloca <3 x i32>, align 16
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%extractVec = shufflevector <3 x float> %a, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
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store <4 x float> %extractVec, ptr %a.addr, align 16
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%extractVec1 = shufflevector <3 x float> %b, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
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store <4 x float> %extractVec1, ptr %b.addr, align 16
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%extractVec3 = shufflevector <3 x i32> %c, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
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store <4 x i32> %extractVec3, ptr %c.addr, align 16
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call void @llvm.lifetime.start.p0(ptr %zero) #2
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store <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, ptr %zero, align 16
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call void @llvm.lifetime.start.p0(ptr %mask) #2
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%loadVec4 = load <4 x i32>, ptr %zero, align 16
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%extractVec6 = shufflevector <4 x i32> %loadVec4, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
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%loadVec48 = load <4 x i32>, ptr %c.addr, align 16
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%extractVec9 = shufflevector <4 x i32> %loadVec48, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
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%cmp = icmp sgt <3 x i32> %extractVec6, %extractVec9
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%sext = sext <3 x i1> %cmp to <3 x i32>
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%extractVec10 = shufflevector <3 x i32> %sext, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
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store <4 x i32> %extractVec10, ptr %mask, align 16
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call void @llvm.lifetime.start.p0(ptr %res) #2
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%loadVec413 = load <4 x i32>, ptr %mask, align 16
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%extractVec14 = shufflevector <4 x i32> %loadVec413, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
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%loadVec416 = load <4 x float>, ptr %b.addr, align 16
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%extractVec17 = shufflevector <4 x float> %loadVec416, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
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%astype = bitcast <3 x float> %extractVec17 to <3 x i32>
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%and = and <3 x i32> %extractVec14, %astype
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%extractVec18 = shufflevector <3 x i32> %and, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
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store <4 x i32> %extractVec18, ptr %res, align 16
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%loadVec421 = load <4 x i32>, ptr %mask, align 16
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%extractVec22 = shufflevector <4 x i32> %loadVec421, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
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%cmp23 = icmp eq <3 x i32> %extractVec22, zeroinitializer
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%sext24 = sext <3 x i1> %cmp23 to <3 x i32>
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%loadVec426 = load <4 x float>, ptr %a.addr, align 16
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%extractVec27 = shufflevector <4 x float> %loadVec426, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
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%astype28 = bitcast <3 x float> %extractVec27 to <3 x i32>
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%and29 = and <3 x i32> %sext24, %astype28
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%loadVec431 = load <4 x i32>, ptr %res, align 16
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%extractVec32 = shufflevector <4 x i32> %loadVec431, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
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%or = or <3 x i32> %and29, %extractVec32
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%astype33 = bitcast <3 x i32> %or to <3 x float>
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call void @llvm.lifetime.end.p0(ptr %res) #2
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call void @llvm.lifetime.end.p0(ptr %mask) #2
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call void @llvm.lifetime.end.p0(ptr %zero) #2
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ret <3 x float> %astype33
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}
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define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) {
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; CHECK-LABEL: @allSignBits_vec(
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; CHECK-NEXT: [[ISNEG1:%.*]] = icmp slt <4 x i8> [[COND:%.*]], zeroinitializer
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; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i8> [[TVAL:%.*]], <4 x i8> [[FVAL:%.*]]
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; CHECK-NEXT: ret <4 x i8> [[SEL]]
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;
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%bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7>
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%not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1>
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%a1 = and <4 x i8> %tval, %bitmask
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%a2 = and <4 x i8> %fval, %not_bitmask
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%sel = or <4 x i8> %a2, %a1
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ret <4 x i8> %sel
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}
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define <4 x i32> @PR42100(<4 x i32> noundef %x, <4 x i32> noundef %min) {
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; CHECK-LABEL: @PR42100(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[X:%.*]], <4 x i32> [[MIN:%.*]])
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; CHECK-NEXT: ret <4 x i32> [[TMP0]]
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;
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entry:
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br label %for.cond
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for.cond:
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%min.addr.0 = phi <4 x i32> [ %min, %entry ], [ %min.addr.1, %for.inc ]
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp ne i32 %i.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%vecext = extractelement <4 x i32> %x, i32 %i.0
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%vecext1 = extractelement <4 x i32> %min.addr.0, i32 %i.0
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%cmp2 = icmp slt i32 %vecext, %vecext1
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br i1 %cmp2, label %if.then, label %if.end
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if.then:
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%vecext3 = extractelement <4 x i32> %x, i32 %i.0
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%vecins = insertelement <4 x i32> %min.addr.0, i32 %vecext3, i32 %i.0
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br label %if.end
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if.end:
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%min.addr.1 = phi <4 x i32> [ %vecins, %if.then ], [ %min.addr.0, %for.body ]
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end:
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ret <4 x i32> %min.addr.0
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}
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declare void @llvm.lifetime.start.p0(ptr nocapture) #1
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declare void @llvm.lifetime.end.p0(ptr nocapture) #1
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