1d9775f684
The canonical form preferred by instcombine is to use 64-bit values for the index when it is a constant. We should try to do the same where possible in the loop vectoriser as this reduces churn in the compiler. It also makes other work easier, such as removing extra unnecessary passes on the RUN line in the test directory which I plan to do afterwards.
75 lines
3.1 KiB
LLVM
75 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -passes=loop-vectorize -S | FileCheck %s
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; Test case for PR44488. Checks that the correct predicates are created for
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; branches where true and false successors are equal. See the checks involving
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; CMP1 and CMP2.
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@v_38 = global i16 12061, align 1
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@v_39 = global i16 11333, align 1
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define i16 @test_true_and_false_branch_equal() {
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; CHECK-LABEL: @test_true_and_false_branch_equal(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE2:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @v_38, align 1
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i16 [[TMP0]], 0
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; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_SREM_IF:%.*]], label [[PRED_SREM_CONTINUE:%.*]]
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; CHECK: pred.srem.if:
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; CHECK-NEXT: [[TMP4:%.*]] = srem i16 5786, [[TMP0]]
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i16> poison, i16 [[TMP4]], i64 0
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; CHECK-NEXT: br label [[PRED_SREM_CONTINUE]]
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; CHECK: pred.srem.continue:
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; CHECK-NEXT: [[TMP6:%.*]] = phi <2 x i16> [ poison, [[VECTOR_BODY]] ], [ [[TMP5]], [[PRED_SREM_IF]] ]
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; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_SREM_IF1:%.*]], label [[PRED_SREM_CONTINUE2]]
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; CHECK: pred.srem.if1:
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; CHECK-NEXT: [[TMP8:%.*]] = srem i16 5786, [[TMP0]]
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; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i16> [[TMP6]], i16 [[TMP8]], i64 1
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; CHECK-NEXT: br label [[PRED_SREM_CONTINUE2]]
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; CHECK: pred.srem.continue2:
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; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x i16> [ [[TMP6]], [[PRED_SREM_CONTINUE]] ], [ [[TMP9]], [[PRED_SREM_IF1]] ]
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; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP3]], <2 x i16> [[TMP10]], <2 x i16> splat (i16 5786)
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; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i16> [[PREDPHI]], i64 1
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; CHECK-NEXT: store i16 [[TMP11]], ptr @v_39, align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12
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; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br label [[FOR_LATCH:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[RV:%.*]] = load i16, ptr @v_39, align 1
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; CHECK-NEXT: ret i16 [[RV]]
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;
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entry:
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br label %for.body
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for.body:
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%i.07 = phi i16 [ 99, %entry ], [ %inc7, %for.latch ]
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%lv = load i16, ptr @v_38, align 1
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%cmp1 = icmp eq i16 %lv, 32767
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br i1 %cmp1, label %cond.end, label %cond.end
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cond.end:
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%cmp2 = icmp eq i16 %lv, 0
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br i1 %cmp2, label %for.latch, label %cond.false4
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cond.false4:
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%rem = srem i16 5786, %lv
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br label %for.latch
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for.latch:
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%cond6 = phi i16 [ %rem, %cond.false4 ], [ 5786, %cond.end ]
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store i16 %cond6, ptr @v_39, align 1
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%inc7 = add nsw i16 %i.07, 1
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%cmp = icmp slt i16 %inc7, 111
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br i1 %cmp, label %for.body, label %exit
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exit:
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%rv = load i16, ptr @v_39, align 1
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ret i16 %rv
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}
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