4cd2db44f7
While in this area I also removed unnecessary annotations for wchar_size and also cleaned up some more function attributes.
228 lines
7.1 KiB
LLVM
228 lines
7.1 KiB
LLVM
; RUN: opt < %s -passes=loop-vectorize -enable-vplan-native-path -debug-only=loop-vectorize --disable-output -S 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; Verify that outer loops annotated only with the expected explicit
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; vectorization hints are collected for vectorization instead of inner loops.
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; Root C/C++ source code for all the test cases
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; void foo(int *a, int *b, int N, int M)
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; {
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; int i, j;
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; #pragma clang loop vectorize(enable)
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; for (i = 0; i < N; i++) {
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; for (j = 0; j < M; j++) {
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; a[i*M+j] = bptr b[i*M+j];
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; }
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; }
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; }
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; Case 1: Annotated outer loop WITH vector width information must be collected.
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; CHECK-LABEL: vector_width
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; CHECK: LV: Loop hints: force=enabled width=4 interleave=0
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; CHECK: LV: We can vectorize this outer loop!
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; CHECK: LV: Using user VF 4 to build VPlans.
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; CHECK-NOT: LV: Loop hints: force=?
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; CHECK-NOT: LV: Found a loop: inner.body
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @vector_width(ptr nocapture %a, ptr nocapture readonly %b, i32 %N, i32 %M) {
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entry:
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%cmp32 = icmp sgt i32 %N, 0
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br i1 %cmp32, label %outer.ph, label %for.end15
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outer.ph:
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%cmp230 = icmp sgt i32 %M, 0
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%0 = sext i32 %M to i64
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%wide.trip.count = zext i32 %M to i64
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%wide.trip.count38 = zext i32 %N to i64
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br label %outer.body
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outer.body:
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%indvars.iv35 = phi i64 [ 0, %outer.ph ], [ %indvars.iv.next36, %outer.inc ]
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br i1 %cmp230, label %inner.ph, label %outer.inc
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inner.ph:
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%1 = mul nsw i64 %indvars.iv35, %0
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br label %inner.body
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inner.body:
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%indvars.iv = phi i64 [ 0, %inner.ph ], [ %indvars.iv.next, %inner.body ]
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%2 = add nsw i64 %indvars.iv, %1
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%arrayidx = getelementptr inbounds i32, ptr %b, i64 %2
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%3 = load i32, ptr %arrayidx, align 4
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%mul8 = mul nsw i32 %3, %3
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%arrayidx12 = getelementptr inbounds i32, ptr %a, i64 %2
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store i32 %mul8, ptr %arrayidx12, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %outer.inc, label %inner.body
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outer.inc:
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%indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1
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%exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38
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br i1 %exitcond39, label %for.end15, label %outer.body, !llvm.loop !6
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for.end15:
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ret void
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}
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; Case 2: Annotated outer loop WITHOUT vector width information must be collected.
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; CHECK-LABEL: case2
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; CHECK: LV: Loop hints: force=enabled width=0 interleave=0
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; CHECK: LV: We can vectorize this outer loop!
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; CHECK: LV: Using VF 1 to build VPlans.
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define void @case2(ptr nocapture %a, ptr nocapture readonly %b, i32 %N, i32 %M) {
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entry:
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%cmp32 = icmp sgt i32 %N, 0
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br i1 %cmp32, label %outer.ph, label %for.end15
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outer.ph:
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%cmp230 = icmp sgt i32 %M, 0
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%0 = sext i32 %M to i64
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%wide.trip.count = zext i32 %M to i64
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%wide.trip.count38 = zext i32 %N to i64
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br label %outer.body
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outer.body:
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%indvars.iv35 = phi i64 [ 0, %outer.ph ], [ %indvars.iv.next36, %outer.inc ]
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br i1 %cmp230, label %inner.ph, label %outer.inc
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inner.ph:
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%1 = mul nsw i64 %indvars.iv35, %0
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br label %inner.body
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inner.body:
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%indvars.iv = phi i64 [ 0, %inner.ph ], [ %indvars.iv.next, %inner.body ]
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%2 = add nsw i64 %indvars.iv, %1
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%arrayidx = getelementptr inbounds i32, ptr %b, i64 %2
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%3 = load i32, ptr %arrayidx, align 4
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%mul8 = mul nsw i32 %3, %3
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%arrayidx12 = getelementptr inbounds i32, ptr %a, i64 %2
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store i32 %mul8, ptr %arrayidx12, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %outer.inc, label %inner.body
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outer.inc:
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%indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1
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%exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38
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br i1 %exitcond39, label %for.end15, label %outer.body, !llvm.loop !9
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for.end15:
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ret void
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}
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; Case 3: Annotated outer loop WITH vector width and interleave information
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; doesn't have to be collected.
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; CHECK-LABEL: case3
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; CHECK-NOT: LV: Loop hints: force=enabled
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; CHECK-NOT: LV: We can vectorize this outer loop!
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; CHECK: LV: Loop hints: force=?
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; CHECK: LV: Found a loop: inner.body
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define void @case3(ptr nocapture %a, ptr nocapture readonly %b, i32 %N, i32 %M) {
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entry:
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%cmp32 = icmp sgt i32 %N, 0
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br i1 %cmp32, label %outer.ph, label %for.end15
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outer.ph:
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%cmp230 = icmp sgt i32 %M, 0
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%0 = sext i32 %M to i64
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%wide.trip.count = zext i32 %M to i64
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%wide.trip.count38 = zext i32 %N to i64
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br label %outer.body
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outer.body:
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%indvars.iv35 = phi i64 [ 0, %outer.ph ], [ %indvars.iv.next36, %outer.inc ]
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br i1 %cmp230, label %inner.ph, label %outer.inc
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inner.ph:
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%1 = mul nsw i64 %indvars.iv35, %0
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br label %inner.body
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inner.body:
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%indvars.iv = phi i64 [ 0, %inner.ph ], [ %indvars.iv.next, %inner.body ]
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%2 = add nsw i64 %indvars.iv, %1
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%arrayidx = getelementptr inbounds i32, ptr %b, i64 %2
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%3 = load i32, ptr %arrayidx, align 4
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%mul8 = mul nsw i32 %3, %3
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%arrayidx12 = getelementptr inbounds i32, ptr %a, i64 %2
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store i32 %mul8, ptr %arrayidx12, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %outer.inc, label %inner.body
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outer.inc:
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%indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1
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%exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38
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br i1 %exitcond39, label %for.end15, label %outer.body, !llvm.loop !11
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for.end15:
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ret void
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}
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; Case 4: Outer loop without any explicit vectorization annotation doesn't have
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; to be collected.
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; CHECK-LABEL: case4
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; CHECK-NOT: LV: Loop hints: force=enabled
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; CHECK-NOT: LV: We can vectorize this outer loop!
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; CHECK: LV: Loop hints: force=?
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; CHECK: LV: Found a loop: inner.body
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define void @case4(ptr nocapture %a, ptr nocapture readonly %b, i32 %N, i32 %M) {
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entry:
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%cmp32 = icmp sgt i32 %N, 0
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br i1 %cmp32, label %outer.ph, label %for.end15
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outer.ph:
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%cmp230 = icmp sgt i32 %M, 0
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%0 = sext i32 %M to i64
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%wide.trip.count = zext i32 %M to i64
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%wide.trip.count38 = zext i32 %N to i64
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br label %outer.body
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outer.body:
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%indvars.iv35 = phi i64 [ 0, %outer.ph ], [ %indvars.iv.next36, %outer.inc ]
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br i1 %cmp230, label %inner.ph, label %outer.inc
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inner.ph:
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%1 = mul nsw i64 %indvars.iv35, %0
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br label %inner.body
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inner.body:
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%indvars.iv = phi i64 [ 0, %inner.ph ], [ %indvars.iv.next, %inner.body ]
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%2 = add nsw i64 %indvars.iv, %1
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%arrayidx = getelementptr inbounds i32, ptr %b, i64 %2
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%3 = load i32, ptr %arrayidx, align 4
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%mul8 = mul nsw i32 %3, %3
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%arrayidx12 = getelementptr inbounds i32, ptr %a, i64 %2
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store i32 %mul8, ptr %arrayidx12, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %outer.inc, label %inner.body
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outer.inc:
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%indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1
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%exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38
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br i1 %exitcond39, label %for.end15, label %outer.body
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for.end15:
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ret void
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}
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; Case 1
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!6 = distinct !{!6, !7, !8}
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!7 = !{!"llvm.loop.vectorize.width", i32 4}
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!8 = !{!"llvm.loop.vectorize.enable", i1 true}
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; Case 2
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!9 = distinct !{!9, !8}
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; Case 3
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!10 = !{!"llvm.loop.interleave.count", i32 2}
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!11 = distinct !{!11, !7, !10, !8}
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