a9eeb151fb
This PR: Fixes a slight off-by-one error in the check for how many bits are allocated for subreg lane masks. If 65 subreg lanes are used, it fails later, but the error message is not clear as to what has occured.
13 lines
404 B
TableGen
13 lines
404 B
TableGen
// RUN: not llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o - 2>&1 | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTarget : Target;
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foreach Index = 0...64 in {
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def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
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}
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def A : Register<"">;
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def TestRC : RegisterClass<"Test", [i32], 0, (add A)>;
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// CHECK: error: Ran out of lanemask bits to represent subregister sub64
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