67 lines
2.7 KiB
TableGen
67 lines
2.7 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def R0 : Register<"r0">;
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def RC : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def MyInstrInfo : InstrInfo;
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def MyTarget : Target {
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let InstructionSet = MyInstrInfo;
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}
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// CHECK-LABEL: case 0:
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// CHECK-NEXT: if (!Check(S, DecodeRCRegisterClass(MI, Decoder)))
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// CHECK-NEXT: return MCDisassembler::Fail;
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 2, 4);
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 0, 2);
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 6, 2) << 2;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 13, 2) << 1;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 17, 1) << 1;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 19, 1) << 3;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x5;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x2;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 26, 2) << 2;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0xa;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 28, 1);
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 30, 1) << 2;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: return S;
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def I : Instruction {
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let OutOperandList = (outs RC:$op0);
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let InOperandList = (ins i32imm:$op1, i32imm:$op2, i32imm:$op3, i32imm:$op4,
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i32imm:$op5, i32imm:$op6, i32imm:$op7, i32imm:$op8);
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let Size = 4;
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bits<32> Inst;
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bits<0> op0; // no init, no variable parts
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bits<4> op1; // no init, 1 variable part
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bits<4> op2; // no init, 2 variable parts
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bits<4> op3 = 0b0000; // zero init, no variable parts
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bits<4> op4 = {0, ?, ?, 0}; // zero init, 1 variable part
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bits<4> op5 = {?, 0, ?, 0}; // zero init, 2 variable parts
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bits<4> op6 = 0b0101; // non-zero init, no variable parts
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bits<4> op7 = {?, ?, 1, 0}; // non-zero init, 1 variable part
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bits<4> op8 = {1, ?, 1, ?}; // non-zero init, 2 variable parts
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let Inst{5...2} = op1;
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let Inst{1...0} = op2{1...0};
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let Inst{7...6} = op2{3...2};
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let Inst{11...8} = op3;
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let Inst{15...12} = op4;
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let Inst{19...16} = op5;
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let Inst{23...20} = op6;
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let Inst{27...24} = op7;
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let Inst{31...28} = op8;
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}
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