734eb95402
I have a downstream target which has 128-bit instructions where some instructions can have large sections of encoding to be determined ahead of time. This results in the island calculations for decoder tables to emit checks over 64-bits. This change will emit multiple separate checks when the island exceeds 64-bits.
39 lines
911 B
TableGen
39 lines
911 B
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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class I<dag outs, dag ins, bits<5> opcode> : Instruction {
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let InOperandList = ins;
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let OutOperandList = outs;
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bits<5> dst;
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bits<5> src0;
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bits<5> src1;
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int Size = 16;
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bits<128> Inst;
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let Inst{4...0} = opcode;
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let Inst{9...5} = dst;
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let Inst{14...10} = src0;
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let Inst{19...15} = src1;
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let Inst{127...20} = 0xdeadbeef;
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}
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def Reg : Register<"reg">;
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def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>;
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def IAdd : I<(outs Regs:$dst), (ins Regs:$src0, Regs:$src1), 0b10101>;
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// CHECK-LABEL: static const uint8_t DecoderTable128[20] = {
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// CHECK-NEXT: OPC_CheckField, 84, 44, 0, // 0: check Inst[127:84] == 0x0
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// CHECK-NEXT: OPC_CheckField, 20, 64, 239, 253, 182, 245, 13,
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def II : InstrInfo;
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def MyTarget : Target {
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let InstructionSet = II;
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}
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