60bdf09654
### Current state We have FilterChooser class, which can be thought of as a **tree of encodings**. Tree nodes are instances of FilterChooser itself, and come in two types: * A node containing single encoding that has *constant* bits in the specified bit range, a.k.a. singleton node. * A node containing only child nodes, where each child represents a set of encodings that have the same *constant* bits in the specified bit range. Either of these nodes can have an additional child, which represents a set of encodings that have some *unknown* bits in the same bit range. As can be seen, the **data structure is very high level**. The encoding tree represented by FilterChooser is then converted into a finite-state machine (FSM), represented as **byte array**. The translation is straightforward: for each node of the tree we emit a sequence of opcodes that check encoding bits and predicates for each encoding. For a singleton node we also emit a terminal "decode" opcode. The translation is done in one go, and this has negative consequences: * We miss optimization opportunities. * We have to use "fixups" when encoding transitions in the FSM since we don't know the size of the data we want to jump over in advance. We have to emit the data first and then fix up the location of the jump. This means the fixup size has to be large enough to encode the longest jump, so **most of the transitions are encoded inefficiently**. * Finally, when converting the FSM into human readable form, we have to **decode the byte array we've just emitted**. This is also done in one go, so we **can't do any pretty printing**. ### This PR We introduce an intermediary data structure, decoder tree, that can be thought as **AST of the decoder program**. This data structure is **low level** and as such allows for optimization and analysis. It resolves all the issues listed above. We now can: * Emit more optimal opcode sequences. * Compute the size of the data to be emitted in advance, avoiding fixups. * Do pretty printing. Serialization is done by a new class, DecoderTableEmitter, which converts the AST into a FSM in **textual form**, streamed right into the output file. ### Results * The new approach immediately resulted in 12% total table size savings across all in-tree targets, without implementing any optimizations on the AST. Many tables observe ~20% size reduction. * The generated file is much more readable. * The implementation is arguably simpler and more straightforward (the diff is only +150~200 lines, which feels rather small for the benefits the change gives).
94 lines
3.3 KiB
TableGen
94 lines
3.3 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s --check-prefixes=CHECK
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;
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def GR64 : RegisterOperand<RegClass>;
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class MyMemOperand<dag sub_ops> : Operand<iPTR> {
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let MIOperandInfo = sub_ops;
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dag Base;
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dag Extension;
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}
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def MemOp16: MyMemOperand<(ops GR64:$reg, i16imm:$offset)>;
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def MemOp32: MyMemOperand<(ops GR64:$reg, i32imm:$offset)>;
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class MyVarInst<MyMemOperand memory_op> : Instruction {
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dag Inst;
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let OutOperandList = (outs GR64:$dst);
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let InOperandList = (ins memory_op:$src);
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}
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def FOO16 : MyVarInst<MemOp16> {
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let Inst = (ascend
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(descend (operand "$dst", 3), 0b01000, (operand "$src.reg", 3)),
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(slice "$src.offset", 15, 0, (decoder "myCustomDecoder"))
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);
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}
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def FOO32 : MyVarInst<MemOp32> {
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let Inst = (ascend
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(descend (operand "$dst", 3), 0b01001,
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(operand "$src.reg", 3, (decoder "myCustomDecoder"))),
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(slice "$src.offset", 31, 16),
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(slice "$src.offset", 15, 0)
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);
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}
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// Instruction length table
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// CHECK: InstrLenTable
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// CHECK: 27,
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// CHECK-NEXT: 43,
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// CHECK-NEXT: };
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// CHECK-LABEL: static const uint8_t DecoderTable43[15] = {
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// CHECK-NEXT: OPC_SwitchField, 3, 5, // 0: switch Inst[7:3] {
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// CHECK-NEXT: 8, 4, // 3: case 0x8: {
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// CHECK-NEXT: OPC_Decode, {{[0-9, ]+}}, 0, // 5: decode to FOO16 using decoder 0
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// CHECK-NEXT: // 5: }
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// CHECK-NEXT: 9, 0, // 9: case 0x9: {
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// CHECK-NEXT: OPC_Decode, {{[0-9, ]+}}, 1, // 11: decode to FOO32 using decoder 1
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// CHECK-NEXT: // 11: }
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// CHECK-NEXT: // 11: } // switch Inst[7:3]
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// CHECK-NEXT: };
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// CHECK: case 0:
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 11, 16);
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// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: return S;
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// CHECK-NEXT: case 1:
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
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// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 11, 16) << 16;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 27, 16);
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: return S;
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// CHECK-LABEL: case OPC_SwitchField: {
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// CHECK: makeUp(insn, Start + Len);
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// CHECK-LABEL: case OPC_CheckField: {
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// CHECK: makeUp(insn, Start + Len);
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// CHECK-LABEL: case OPC_Decode: {
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// CHECK: Len = InstrLenTable[Opc];
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// CHECK-NEXT: makeUp(insn, Len);
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