cbd99c55a3
Tablegen would generate code to access TargetResourceIndices with processor ID. The TargetProcResourceIndexStart[] array is generated for each processor which has itineraries. The processor which doesn't has itineraries is excluded from the array. When a target has mixed processors, the processor ID may exceed the array size and cause the error. This patch is to generate a table mapping processor with itineraries to resource index, so that scheduler can get the correct resource index with processor ID.
40 lines
1.2 KiB
TableGen
40 lines
1.2 KiB
TableGen
// RUN: llvm-tblgen -gen-dfa-packetizer -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTarget : Target;
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def TestSchedModel : SchedMachineModel {
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let CompleteModel = 0;
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}
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def TestProcessor1 : ProcessorModel<"testprocessor1", TestSchedModel, []>;
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def FU0 : FuncUnit;
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def FU1 : FuncUnit;
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def OP0 : InstrItinClass;
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def OP1 : InstrItinClass;
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def Itin {
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list<InstrItinData> ItinList = [
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InstrItinData<OP0, [InstrStage<1, [FU0]>]>,
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InstrItinData<OP1, [InstrStage<1, [FU1]>]>,
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];
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}
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// CHECK: int TestTargetGetResourceIndex(unsigned ProcID) {
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// CHECK-NEXT: static const unsigned TestTargetProcIdToProcResourceIdxTable[][2] = {
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// CHECK-NEXT: { 2, 1 }, // TestItinerariesModel
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// CHECK-NEXT: };
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// CHECK-NEXT: auto It = llvm::lower_bound(TestTargetProcIdToProcResourceIdxTable, ProcID,
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// CHECK-NEXT: [](const unsigned LHS[], unsigned Val) { return LHS[0] < Val; });
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// CHECK-NEXT: assert(*It[0] == ProcID);
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// CHECK-NEXT: return (*It)[1];
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// CHECK-NEXT: }
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// CHECK: unsigned Index = TestTargetGetResourceIndex(IID->SchedModel.ProcID);
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def TestItineraries: ProcessorItineraries<[], [], Itin.ItinList>;
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def TestProcessor2 : Processor<"testprocessor2", TestItineraries, []>;
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