79d2444dae
Dump the Artificial flag for RegisterClasses, SubRegIndices and Registers. To avoid clutter it is only dumped when the flag is set (has value 1).
64 lines
1.8 KiB
TableGen
64 lines
1.8 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o - 2>&1 >/dev/null | FileCheck %s --implicit-check-not=RegisterClass
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include "llvm/Target/Target.td"
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def lo : SubRegIndex<0, 32>;
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def hi : SubRegIndex<32, 32>;
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def R0 : Register<"r0">;
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def R1 : Register<"r1">;
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def A : Register<"a"> {
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let isArtificial = 1;
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}
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def D0 : Register<"d0"> {
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let SubRegs = [R0, R1];
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let SubRegIndices = [lo, hi];
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}
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// Same artificial registers can participate in classes of
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// registers and their sub-registers.
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def RA : RegisterClass<"R", [i32], 32, (add R0, R1, A)>;
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def DA : RegisterClass<"D", [i64], 64, (add D0, A)>;
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// Make sure there are no DA_and_RA and DA_with_hi kind of
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// classes that only contain artificial registers or are inferred
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// copies of already existing register classes that only differ
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// in the presence of artificial regsiters.
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//
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// CHECK-LABEL: RegisterClass RA:
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// CHECK-NEXT: SpillSize:
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// CHECK-NEXT: SpillAlignment:
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// CHECK-NEXT: NumRegs:
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// CHECK-NEXT: LaneMask:
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// CHECK-NEXT: HasDisjunctSubRegs:
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// CHECK-NEXT: CoveredBySubRegs:
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// CHECK-NEXT: Allocatable:
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// CHECK-NEXT: AllocationPriority:
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// CHECK-NEXT: BaseClassOrder:
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// CHECK-NEXT: Regs: A R0 R1{{$}}
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// CHECK-NEXT: SubClasses: RA{{$}}
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//
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// CHECK-LABEL: RegisterClass DA:
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// CHECK-NEXT: SpillSize:
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// CHECK-NEXT: SpillAlignment:
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// CHECK-NEXT: NumRegs:
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// CHECK-NEXT: LaneMask:
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// CHECK-NEXT: HasDisjunctSubRegs:
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// CHECK-NEXT: CoveredBySubRegs:
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// CHECK-NEXT: Allocatable:
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// CHECK-NEXT: AllocationPriority:
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// CHECK-NEXT: BaseClassOrder:
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// CHECK-NEXT: Regs: A D0{{$}}
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// CHECK-NEXT: SubClasses: DA{{$}}
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//
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// CHECK-LABEL: Register A:
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// CHECK-NEXT: CostPerUse: 0
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// CHECK-NEXT: CoveredBySubregs: 0
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// CHECK-NEXT: HasDisjunctSubRegs: 0
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// CHECK-NEXT: RegUnit 0
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// CHECK-NEXT: Artificial: 1
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def TestTarget : Target;
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