2f422a52fd
This PR implements the prefetch insertion in the InsertCodePrefetch pass based on the [RFC](https://discourse.llvm.org/t/rfc-code-prefetch-insertion/88668). If the prefetch target is not defined in the same module (i.e, prefetch target function is not defined in the same module), we emit a fallback weak symbol after the prefetch instruction so that if the symbol is not ever defined, we don't get undefined symbol error and the prefetch instruction prefetches the next address: ``` prefetchit1 __llvm_prefetch_target_foo(%rip) .weak __llvm_prefetch_target_foo __llvm_prefetch_target_foo: ``` The weak symbol semantic is tied to ELF, so this makes this PR target-dependent.
87 lines
2.9 KiB
LLVM
87 lines
2.9 KiB
LLVM
;; Check prefetch directives in basic block section profiles.
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;;
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;; Specify the bb sections profile:
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; RUN: echo 'v1' > %t
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; RUN: echo 'f foo' >> %t
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; RUN: echo 't 0,0' >> %t
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; RUN: echo 't 1,0' >> %t
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; RUN: echo 't 1,1' >> %t
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; RUN: echo 't 2,1' >> %t
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; RUN: echo 't 3,0' >> %t
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; RUN: echo 't 3,1' >> %t
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; RUN: echo 'i 3,0 bar,0,0' >> %t
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; RUN: echo 'i 2,1 foo,1,0' >> %t
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; RUN: echo 'i 1,1 extfunc,5,5' >> %t
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; RUN: echo 'i 1,1 bar,0,0' >> %t
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; RUN: echo 'f bar' >> %t
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; RUN: echo 't 0,0' >> %t
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; RUN: echo 't 21,1' >> %t
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; RUN: echo 'i 0,1 foo,0,0' >> %t
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; RUN: echo 'f qux' >> %t
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; RUN: echo 't 0,0' >> %t
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; RUN: echo 't 0,1' >> %t
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;;
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; RUN: llc < %s -mtriple=x86_64-pc-linux -asm-verbose=false -function-sections -basic-block-sections=%t -O0 | FileCheck %s
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define void @foo(i1 %arg) nounwind {
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br i1 %arg, label %cond.true, label %cond.false
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; CHECK: foo:
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; CHECK-NEXT: .globl __llvm_prefetch_target_foo_0_0
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; CHECK-NEXT: __llvm_prefetch_target_foo_0_0:
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cond.true: ; preds = %1
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call i32 @bar()
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br label %end
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; CHECK: .globl __llvm_prefetch_target_foo_1_0
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; CHECK-NEXT: __llvm_prefetch_target_foo_1_0:
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; CHECK-NEXT: callq bar@PLT
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; CHECK-NEXT: .globl __llvm_prefetch_target_foo_1_1
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; CHECK-NEXT: __llvm_prefetch_target_foo_1_1:
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; CHECK-NEXT: prefetchit1 __llvm_prefetch_target_extfunc_5_5(%rip)
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; CHECK-NEXT: .weak __llvm_prefetch_target_extfunc_5_5
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; CHECK-NEXT: __llvm_prefetch_target_extfunc_5_5:
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; CHECK-NEXT: prefetchit1 __llvm_prefetch_target_bar_0_0(%rip)
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cond.false: ; preds = %1
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call i32 @baz()
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br label %end
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; CHECK: callq baz@PLT
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; CHECK-NEXT: .globl __llvm_prefetch_target_foo_2_1
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; CHECK-NEXT: __llvm_prefetch_target_foo_2_1:
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; CHECK-NEXT: prefetchit1 __llvm_prefetch_target_foo_1_0(%rip)
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end: ; preds = %11, %9
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ret void
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; CHECK: .LBB0_3:
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; CHECK-NEXT: .globl __llvm_prefetch_target_foo_3_0
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; CHECK-NEXT: __llvm_prefetch_target_foo_3_0:
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; CHECK-NEXT: prefetchit1 __llvm_prefetch_target_bar_0_0(%rip)
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; CHECK: .globl __llvm_prefetch_target_foo_3_1
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; CHECK-NEXT: __llvm_prefetch_target_foo_3_1:
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}
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define weak i32 @bar() nounwind {
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%call = call i32 @baz()
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ret i32 %call
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; CHECK: bar:
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; CHECK-NEXT: .weak __llvm_prefetch_target_bar_21_1
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; CHECK-NEXT: __llvm_prefetch_target_bar_21_1:
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; CHECK-NEXT: .weak __llvm_prefetch_target_bar_0_0
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; CHECK-NEXT: __llvm_prefetch_target_bar_0_0:
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; CHECK: callq baz@PLT
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; CHECK-NEXT: prefetchit1 __llvm_prefetch_target_foo_0_0(%rip)
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}
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define internal i32 @qux() nounwind {
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%call = call i32 @baz()
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ret i32 %call
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; CHECK: qux:
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; CHECK-NEXT: .globl __llvm_prefetch_target_qux_0_0
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; CHECK-NEXT: __llvm_prefetch_target_qux_0_0:
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; CHECK: callq baz@PLT
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; CHECK-NEXT: .globl __llvm_prefetch_target_qux_0_1
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; CHECK-NEXT: __llvm_prefetch_target_qux_0_1:
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}
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declare i32 @baz()
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