5e0a06b34d
Moving these into the middle-end pipeline will allow for additional optimization of the expansion result, such as CSE of redundant loads (c.f. https://godbolt.org/z/bEna4Md9r). For now, we conservatively place the passes at the end of the middle-end pipeline, so we mostly don't benefit from additional optimizations yet. The pipeline position will be moved in a future change. This builds on work done by legrosbuffle in https://reviews.llvm.org/D60318. --------- Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
88 lines
3.2 KiB
LLVM
88 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes=expand-memcmp -mtriple=wasm32-unknown-unknown -mattr=+simd128 -S < %s | llc -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
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target triple = "wasm32-unknown-unknown"
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declare i32 @memcmp(ptr, ptr, i32)
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define i1 @setcc_load(ptr %a, ptr %b) {
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; CHECK-LABEL: setcc_load:
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; CHECK: .functype setcc_load (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: v128.load $push1=, 0($0):p2align=0
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; CHECK-NEXT: v128.load $push0=, 0($1):p2align=0
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; CHECK-NEXT: i8x16.eq $push2=, $pop1, $pop0
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; CHECK-NEXT: i8x16.all_true $push3=, $pop2
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; CHECK-NEXT: return $pop3
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%cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
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%res = icmp eq i32 %cmp_16, 0
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ret i1 %res
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}
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; INFO: Negative test: noimplicitfloat disables simd
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define i1 @setcc_load_should_not_vectorize(ptr %a, ptr %b) noimplicitfloat {
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; CHECK-LABEL: setcc_load_should_not_vectorize:
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; CHECK: .functype setcc_load_should_not_vectorize (i32, i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i64.load $push4=, 0($0):p2align=0
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; CHECK-NEXT: i64.load $push3=, 0($1):p2align=0
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; CHECK-NEXT: i64.xor $push5=, $pop4, $pop3
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; CHECK-NEXT: i64.load $push1=, 8($0):p2align=0
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; CHECK-NEXT: i64.load $push0=, 8($1):p2align=0
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; CHECK-NEXT: i64.xor $push2=, $pop1, $pop0
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; CHECK-NEXT: i64.or $push6=, $pop5, $pop2
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; CHECK-NEXT: i64.eqz $push7=, $pop6
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; CHECK-NEXT: return $pop7
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%cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
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%res = icmp eq i32 %cmp_16, 0
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ret i1 %res
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}
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define i1 @setcc_eq_const_i128(ptr %ptr) {
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; CHECK-LABEL: setcc_eq_const_i128:
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; CHECK: .functype setcc_eq_const_i128 (i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: v128.load $push0=, 0($0)
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; CHECK-NEXT: v128.const $push1=, 6, 0
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; CHECK-NEXT: i8x16.eq $push2=, $pop0, $pop1
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; CHECK-NEXT: i8x16.all_true $push3=, $pop2
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; CHECK-NEXT: return $pop3
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%l = load i128, ptr %ptr
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%res = icmp eq i128 %l, 6
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ret i1 %res
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}
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define i1 @setcc_ne_const_i128(ptr %ptr) {
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; CHECK-LABEL: setcc_ne_const_i128:
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; CHECK: .functype setcc_ne_const_i128 (i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: v128.load $push0=, 0($0)
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; CHECK-NEXT: v128.const $push1=, 16, 0
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; CHECK-NEXT: i8x16.ne $push2=, $pop0, $pop1
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; CHECK-NEXT: v128.any_true $push3=, $pop2
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; CHECK-NEXT: return $pop3
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%l = load i128, ptr %ptr
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%res = icmp ne i128 %l, 16
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ret i1 %res
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}
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; INFO: Negative test: only eq and ne works
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define i1 @setcc_slt_const_i128(ptr %ptr) {
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; CHECK-LABEL: setcc_slt_const_i128:
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; CHECK: .functype setcc_slt_const_i128 (i32) -> (i32)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: i64.load $push2=, 0($0)
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; CHECK-NEXT: i64.const $push3=, 25
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; CHECK-NEXT: i64.lt_u $push4=, $pop2, $pop3
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; CHECK-NEXT: i64.load $push8=, 8($0)
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; CHECK-NEXT: local.tee $push7=, $1=, $pop8
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; CHECK-NEXT: i64.const $push0=, 0
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; CHECK-NEXT: i64.lt_s $push1=, $pop7, $pop0
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; CHECK-NEXT: i64.eqz $push5=, $1
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; CHECK-NEXT: i32.select $push6=, $pop4, $pop1, $pop5
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; CHECK-NEXT: return $pop6
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%l = load i128, ptr %ptr
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%res = icmp slt i128 %l, 25
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ret i1 %res
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}
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