c999e9a4fe
- Make v8f16 a legal type so that arguments can be passed in vector registers. Handle fp16 vectors so that they have the same ABI as other fp vectors. - Set the preferred vector action for fp16 vectors to "split". This will scalarize all operations, which is not always necessary (like with memory operations), but it avoids the superfluous operations that result after first widening and then scalarizing a narrow vector (like v4f16). Fixes #168992
288 lines
10 KiB
LLVM
288 lines
10 KiB
LLVM
; Test usage of VBLEND on z17.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
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define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
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; CHECK-LABEL: f1:
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; CHECK: vblendb %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <16 x i8> %val1, zeroinitializer
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%ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
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ret <16 x i8> %ret
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}
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define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
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; CHECK-LABEL: f2:
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; CHECK: vblendb %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <16 x i8> %val1, zeroinitializer
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%ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
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ret <16 x i8> %ret
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}
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define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
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; CHECK-LABEL: f3:
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; CHECK: vblendb %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%mask = and <16 x i8> %val1, <i8 128, i8 128, i8 128, i8 128,
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i8 128, i8 128, i8 128, i8 128,
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i8 128, i8 128, i8 128, i8 128,
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i8 128, i8 128, i8 128, i8 128>;
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%cmp = icmp ne <16 x i8> %mask, zeroinitializer
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%ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
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ret <16 x i8> %ret
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}
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define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
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; CHECK-LABEL: f4:
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; CHECK: vblendb %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%mask = and <16 x i8> %val1, <i8 128, i8 128, i8 128, i8 128,
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i8 128, i8 128, i8 128, i8 128,
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i8 128, i8 128, i8 128, i8 128,
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i8 128, i8 128, i8 128, i8 128>;
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%cmp = icmp eq <16 x i8> %mask, zeroinitializer
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%ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
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ret <16 x i8> %ret
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}
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define <8 x i16> @f5(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
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; CHECK-LABEL: f5:
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; CHECK: vblendh %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <8 x i16> %val1, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
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ret <8 x i16> %ret
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}
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define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
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; CHECK-LABEL: f6:
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; CHECK: vblendh %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <8 x i16> %val1, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
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ret <8 x i16> %ret
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}
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define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
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; CHECK-LABEL: f7:
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; CHECK: vblendh %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%mask = and <8 x i16> %val1, <i16 32768, i16 32768, i16 32768, i16 32768,
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i16 32768, i16 32768, i16 32768, i16 32768>;
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%cmp = icmp ne <8 x i16> %mask, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
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ret <8 x i16> %ret
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}
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define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
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; CHECK-LABEL: f8:
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; CHECK: vblendh %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%mask = and <8 x i16> %val1, <i16 32768, i16 32768, i16 32768, i16 32768,
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i16 32768, i16 32768, i16 32768, i16 32768>;
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%cmp = icmp eq <8 x i16> %mask, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
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ret <8 x i16> %ret
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}
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define <4 x i32> @f9(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
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; CHECK-LABEL: f9:
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; CHECK: vblendf %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <4 x i32> %val1, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
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ret <4 x i32> %ret
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}
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define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
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; CHECK-LABEL: f10:
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; CHECK: vblendf %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <4 x i32> %val1, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
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ret <4 x i32> %ret
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}
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define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
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; CHECK-LABEL: f11:
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; CHECK: vblendf %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
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i32 2147483648, i32 2147483648>;
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%cmp = icmp ne <4 x i32> %mask, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
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ret <4 x i32> %ret
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}
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define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
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; CHECK-LABEL: f12:
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; CHECK: vblendf %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
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i32 2147483648, i32 2147483648>;
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%cmp = icmp eq <4 x i32> %mask, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
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ret <4 x i32> %ret
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}
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define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
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; CHECK-LABEL: f13:
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; CHECK: vblendg %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <2 x i64> %val1, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
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ret <2 x i64> %ret
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}
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define <2 x i64> @f14(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
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; CHECK-LABEL: f14:
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; CHECK: vblendg %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <2 x i64> %val1, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
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ret <2 x i64> %ret
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}
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define <2 x i64> @f15(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
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; CHECK-LABEL: f15:
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; CHECK: vblendg %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%mask = and <2 x i64> %val1, <i64 9223372036854775808,
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i64 9223372036854775808>;
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%cmp = icmp ne <2 x i64> %mask, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
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ret <2 x i64> %ret
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}
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define <2 x i64> @f16(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
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; CHECK-LABEL: f16:
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; CHECK: vblendg %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%mask = and <2 x i64> %val1, <i64 9223372036854775808,
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i64 9223372036854775808>;
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%cmp = icmp eq <2 x i64> %mask, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
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ret <2 x i64> %ret
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}
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define <8 x half> @f17(<8 x i16> %val1, <8 x half> %val2, <8 x half> %val3) {
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; CHECK-LABEL: f17:
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; CHECK: vblendh %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <8 x i16> %val1, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x half> %val2, <8 x half> %val3
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ret <8 x half> %ret
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}
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define <8 x half> @f18(<8 x i16> %val1, <8 x half> %val2, <8 x half> %val3) {
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; CHECK-LABEL: f18:
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; CHECK: vblendh %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <8 x i16> %val1, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x half> %val2, <8 x half> %val3
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ret <8 x half> %ret
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}
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define <8 x half> @f19(<8 x i16> %val1, <8 x half> %val2, <8 x half> %val3) {
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; CHECK-LABEL: f19:
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; CHECK: vblendh %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%mask = and <8 x i16> %val1, <i16 32768, i16 32768, i16 32768, i16 32768,
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i16 32768, i16 32768, i16 32768, i16 32768>
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%cmp = icmp ne <8 x i16> %mask, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x half> %val2, <8 x half> %val3
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ret <8 x half> %ret
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}
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define <8 x half> @f20(<8 x i16> %val1, <8 x half> %val2, <8 x half> %val3) {
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; CHECK-LABEL: f20:
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; CHECK: vblendh %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%mask = and <8 x i16> %val1, <i16 32768, i16 32768, i16 32768, i16 32768,
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i16 32768, i16 32768, i16 32768, i16 32768>
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%cmp = icmp eq <8 x i16> %mask, zeroinitializer
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%ret = select <8 x i1> %cmp, <8 x half> %val2, <8 x half> %val3
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ret <8 x half> %ret
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}
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define <4 x float> @f21(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
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; CHECK-LABEL: f21:
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; CHECK: vblendf %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <4 x i32> %val1, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
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ret <4 x float> %ret
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}
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define <4 x float> @f22(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
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; CHECK-LABEL: f22:
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; CHECK: vblendf %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <4 x i32> %val1, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
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ret <4 x float> %ret
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}
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define <4 x float> @f23(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
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; CHECK-LABEL: f23:
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; CHECK: vblendf %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
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i32 2147483648, i32 2147483648>;
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%cmp = icmp ne <4 x i32> %mask, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
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ret <4 x float> %ret
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}
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define <4 x float> @f24(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
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; CHECK-LABEL: f24:
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; CHECK: vblendf %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
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i32 2147483648, i32 2147483648>;
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%cmp = icmp eq <4 x i32> %mask, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
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ret <4 x float> %ret
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}
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define <2 x double> @f25(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
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; CHECK-LABEL: f25:
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; CHECK: vblendg %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <2 x i64> %val1, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
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ret <2 x double> %ret
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}
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define <2 x double> @f26(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
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; CHECK-LABEL: f26:
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; CHECK: vblendg %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <2 x i64> %val1, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
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ret <2 x double> %ret
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}
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define <2 x double> @f27(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
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; CHECK-LABEL: f27:
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; CHECK: vblendg %v24, %v26, %v28, %v24
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; CHECK-NEXT: br %r14
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%mask = and <2 x i64> %val1, <i64 9223372036854775808,
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i64 9223372036854775808>;
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%cmp = icmp ne <2 x i64> %mask, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
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ret <2 x double> %ret
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}
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define <2 x double> @f28(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
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; CHECK-LABEL: f28:
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; CHECK: vblendg %v24, %v28, %v26, %v24
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; CHECK-NEXT: br %r14
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%mask = and <2 x i64> %val1, <i64 9223372036854775808,
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i64 9223372036854775808>;
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%cmp = icmp eq <2 x i64> %mask, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
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ret <2 x double> %ret
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}
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