56a4315ee0
This is a relatively simple strategy as it is omitting any heuristics for liveness and register pressure reduction. This works well as the SystemZ ISel scheduler is using Sched::RegPressure which gives a good input order to begin with. It is trying harder with biasing phys regs than GenericScheduler as it also considers other instructions such as immediate loads directly into phys-regs produced by the register coalescer. This can hopefully be refactored into MachineScheduler.cpp. It has a latency heuristic that is slightly different from the one in GenericScheduler: It is activated for a specific type of region that have many "data sequences" consisting of SUs connected only with a single data-edge that are next to each other in the input order. This is only 3% of all the scheduling regions, but when activated it is applied on all the candidates (not just once per cycle). At the same time it is a bit more careful by checking not only the SU Height against the scheduled latency but also its Depth against the remaining latency. It reuses the GenericScheduler handling of weak edges to help copy coalescing. It also helps with compare zero elimination as it tries to put a CC-defining instruction that produces the compare source value above the compare before any other instruction clobbering CC or the value. This work was started after observing heavy spilling in Cactus, which was actually *caused* by GenericScheduler - disabling it (no pre-RA scheduling) remedied it and gave a 7% improvement in performance on that benchmark. Many different versions have been tried which has evolved into this initial simplistic MachineSchedStrategy that does relatively little and yet achieves double-digit improvements on Cactus and Imagick compared to GenericSched (which is OTOH 3% better on Blender). There will hopefully be more improvements added later on as there seems to be potential for it. It would be very interesting to have other OOO targets try this as well and perhaps make this available in MachineScheduler.cpp (A first attempt with improving the pre-RA scheduling was made with #90181, which however did not materialize in anything actually useful.)
157 lines
4.4 KiB
LLVM
157 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test 128-bit shift right arithmetic in vector registers on z13
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Shift right arithmetic immediate (general case).
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define i128 @f1(i128 %a) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepib %v1, 100
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = ashr i128 %a, 100
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ret i128 %res
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}
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; Shift right arithmetic immediate (< 8 bits).
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define i128 @f2(i128 %a) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepib %v1, 7
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = ashr i128 %a, 7
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ret i128 %res
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}
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; Shift right arithmetic immediate (full bytes).
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define i128 @f3(i128 %a) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepib %v1, 32
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = ashr i128 %a, 32
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ret i128 %res
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}
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; Shift right arithmetic variable.
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define i128 @f4(i128 %a, i128 %sh) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: l %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = ashr i128 %a, %sh
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ret i128 %res
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}
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; Test removal of AND mask with only bottom 7 bits set.
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define i128 @f5(i128 %a, i128 %sh) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: l %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 127
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%shift = ashr i128 %a, %and
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ret i128 %shift
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}
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; Test removal of AND mask including but not limited to bottom 7 bits.
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define i128 @f6(i128 %a, i128 %sh) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: l %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 511
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%shift = ashr i128 %a, %and
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ret i128 %shift
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}
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; Test that AND is not removed when some lower 7 bits are not set.
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define i128 @f7(i128 %a, i128 %sh) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lhi %r0, 63
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; CHECK-NEXT: n %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 63
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%shift = ashr i128 %a, %and
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ret i128 %shift
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}
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; Test that AND with two register operands is not affected.
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define i128 @f8(i128 %a, i128 %b, i128 %sh) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vl %v2, 0(%r5), 3
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; CHECK-NEXT: vn %v1, %v2, %v1
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; CHECK-NEXT: vlgvf %r0, %v1, 3
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrab %v0, %v0, %v1
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; CHECK-NEXT: vsra %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, %b
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%shift = ashr i128 %a, %and
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ret i128 %shift
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}
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; Test that AND is not entirely removed if the result is reused.
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define i128 @f9(i128 %a, i128 %sh) {
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; CHECK-LABEL: f9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: larl %r1, .LCPI8_0
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r1), 3
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; CHECK-NEXT: vn %v0, %v0, %v1
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; CHECK-NEXT: vlgvf %r0, %v0, 3
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v2, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrab %v2, %v2, %v1
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; CHECK-NEXT: vsra %v1, %v2, %v1
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; CHECK-NEXT: vaq %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 127
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%shift = ashr i128 %a, %and
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%reuse = add i128 %and, %shift
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ret i128 %reuse
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}
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