261 lines
7.8 KiB
LLVM
261 lines
7.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Test usage of VACC/VSCBI.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=BASELINE
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
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define i128 @i128_subc_1(i128 %a, i128 %b) unnamed_addr {
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; BASELINE-LABEL: i128_subc_1:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)
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; BASELINE-NEXT: .cfi_offset %r14, -48
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; BASELINE-NEXT: .cfi_offset %r15, -40
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; BASELINE-NEXT: lg %r5, 0(%r4)
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; BASELINE-NEXT: lg %r14, 0(%r3)
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; BASELINE-NEXT: lg %r1, 8(%r3)
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; BASELINE-NEXT: clgr %r14, %r5
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: clg %r1, 8(%r4)
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; BASELINE-NEXT: ipm %r1
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; BASELINE-NEXT: cgrjlh %r14, %r5, .LBB0_2
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; BASELINE-NEXT: # %bb.1:
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; BASELINE-NEXT: xilf %r1, 4294967295
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; BASELINE-NEXT: risbg %r0, %r1, 63, 191, 36
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; BASELINE-NEXT: j .LBB0_3
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; BASELINE-NEXT: .LBB0_2:
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; BASELINE-NEXT: xilf %r0, 4294967295
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; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 36
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; BASELINE-NEXT: .LBB0_3:
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; BASELINE-NEXT: llgfr %r0, %r0
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_subc_1:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v0, 0(%r4), 3
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; Z13-NEXT: vl %v1, 0(%r3), 3
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; Z13-NEXT: vscbiq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%cmp = icmp uge i128 %a, %b
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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define i128 @i128_subc_2(i128 %a, i128 %b) unnamed_addr {
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; BASELINE-LABEL: i128_subc_2:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)
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; BASELINE-NEXT: .cfi_offset %r14, -48
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; BASELINE-NEXT: .cfi_offset %r15, -40
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; BASELINE-NEXT: lg %r5, 0(%r4)
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; BASELINE-NEXT: lg %r14, 0(%r3)
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; BASELINE-NEXT: lg %r0, 8(%r3)
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; BASELINE-NEXT: clgr %r14, %r5
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; BASELINE-NEXT: ipm %r1
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; BASELINE-NEXT: clg %r0, 8(%r4)
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: cgrjlh %r14, %r5, .LBB1_2
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; BASELINE-NEXT: # %bb.1:
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; BASELINE-NEXT: afi %r0, -536870912
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; BASELINE-NEXT: srl %r0, 31
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; BASELINE-NEXT: j .LBB1_3
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; BASELINE-NEXT: .LBB1_2:
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; BASELINE-NEXT: afi %r1, -536870912
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; BASELINE-NEXT: srl %r1, 31
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; BASELINE-NEXT: lr %r0, %r1
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; BASELINE-NEXT: .LBB1_3:
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; BASELINE-NEXT: llgfr %r0, %r0
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_subc_2:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v0, 0(%r3), 3
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; Z13-NEXT: vl %v1, 0(%r4), 3
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; Z13-NEXT: vscbiq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%cmp = icmp ule i128 %a, %b
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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define i128 @i128_addc_1(i128 %a, i128 %b) {
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; BASELINE-LABEL: i128_addc_1:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: lg %r0, 8(%r3)
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; BASELINE-NEXT: lg %r1, 0(%r3)
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; BASELINE-NEXT: alg %r0, 8(%r4)
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; BASELINE-NEXT: alcg %r1, 0(%r4)
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_addc_1:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v0, 0(%r4), 3
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; Z13-NEXT: vl %v1, 0(%r3), 3
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; Z13-NEXT: vaccq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%sum = add i128 %a, %b
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%cmp = icmp ult i128 %sum, %a
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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define i128 @i128_addc_2(i128 %a, i128 %b) {
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; BASELINE-LABEL: i128_addc_2:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: lg %r0, 8(%r3)
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; BASELINE-NEXT: lg %r1, 0(%r3)
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; BASELINE-NEXT: alg %r0, 8(%r4)
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; BASELINE-NEXT: alcg %r1, 0(%r4)
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_addc_2:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v0, 0(%r4), 3
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; Z13-NEXT: vl %v1, 0(%r3), 3
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; Z13-NEXT: vaccq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%sum = add i128 %a, %b
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%cmp = icmp ult i128 %sum, %b
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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define i128 @i128_addc_3(i128 %a, i128 %b) {
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; BASELINE-LABEL: i128_addc_3:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: lg %r0, 8(%r3)
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; BASELINE-NEXT: lg %r1, 0(%r3)
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; BASELINE-NEXT: alg %r0, 8(%r4)
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; BASELINE-NEXT: alcg %r1, 0(%r4)
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_addc_3:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v0, 0(%r4), 3
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; Z13-NEXT: vl %v1, 0(%r3), 3
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; Z13-NEXT: vaccq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%sum = add i128 %a, %b
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%cmp = icmp ugt i128 %a, %sum
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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define i128 @i128_addc_4(i128 %a, i128 %b) {
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; BASELINE-LABEL: i128_addc_4:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: lg %r0, 8(%r3)
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; BASELINE-NEXT: lg %r1, 0(%r3)
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; BASELINE-NEXT: alg %r0, 8(%r4)
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; BASELINE-NEXT: alcg %r1, 0(%r4)
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_addc_4:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v0, 0(%r4), 3
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; Z13-NEXT: vl %v1, 0(%r3), 3
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; Z13-NEXT: vaccq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%sum = add i128 %a, %b
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%cmp = icmp ugt i128 %b, %sum
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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define i128 @i128_addc_xor(i128 %a, i128 %b) {
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; BASELINE-LABEL: i128_addc_xor:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: lg %r0, 8(%r4)
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; BASELINE-NEXT: lg %r1, 0(%r4)
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; BASELINE-NEXT: alg %r0, 8(%r3)
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; BASELINE-NEXT: alcg %r1, 0(%r3)
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_addc_xor:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v0, 0(%r3), 3
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; Z13-NEXT: vl %v1, 0(%r4), 3
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; Z13-NEXT: vaccq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%b.not = xor i128 %b, -1
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%cmp = icmp ugt i128 %a, %b.not
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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define i128 @i128_addc_xor_inv(i128 %a, i128 %b) {
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; BASELINE-LABEL: i128_addc_xor_inv:
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; BASELINE: # %bb.0:
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; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)
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; BASELINE-NEXT: .cfi_offset %r14, -48
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; BASELINE-NEXT: .cfi_offset %r15, -40
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; BASELINE-NEXT: lg %r5, 0(%r3)
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; BASELINE-NEXT: lghi %r14, -1
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; BASELINE-NEXT: xg %r14, 0(%r4)
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; BASELINE-NEXT: lghi %r1, -1
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; BASELINE-NEXT: xg %r1, 8(%r4)
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; BASELINE-NEXT: clgr %r5, %r14
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; BASELINE-NEXT: ipm %r0
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; BASELINE-NEXT: clg %r1, 8(%r3)
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; BASELINE-NEXT: ipm %r1
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; BASELINE-NEXT: cgrjlh %r5, %r14, .LBB7_2
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; BASELINE-NEXT: # %bb.1:
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; BASELINE-NEXT: xilf %r1, 4294967295
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; BASELINE-NEXT: risbg %r0, %r1, 63, 191, 36
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; BASELINE-NEXT: j .LBB7_3
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; BASELINE-NEXT: .LBB7_2:
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; BASELINE-NEXT: afi %r0, -536870912
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; BASELINE-NEXT: srl %r0, 31
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; BASELINE-NEXT: .LBB7_3:
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; BASELINE-NEXT: llgfr %r0, %r0
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; BASELINE-NEXT: stg %r0, 8(%r2)
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; BASELINE-NEXT: mvghi 0(%r2), 0
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; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)
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; BASELINE-NEXT: br %r14
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;
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; Z13-LABEL: i128_addc_xor_inv:
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; Z13: # %bb.0:
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; Z13-NEXT: vl %v1, 0(%r4), 3
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; Z13-NEXT: vl %v0, 0(%r3), 3
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; Z13-NEXT: vno %v1, %v1, %v1
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; Z13-NEXT: vscbiq %v0, %v1, %v0
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; Z13-NEXT: vst %v0, 0(%r2), 3
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; Z13-NEXT: br %r14
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%b.not = xor i128 %b, -1
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%cmp = icmp ule i128 %a, %b.not
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%ext = zext i1 %cmp to i128
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ret i128 %ext
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}
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