c999e9a4fe
- Make v8f16 a legal type so that arguments can be passed in vector registers. Handle fp16 vectors so that they have the same ABI as other fp vectors. - Set the preferred vector action for fp16 vectors to "split". This will scalarize all operations, which is not always necessary (like with memory operations), but it avoids the superfluous operations that result after first widening and then scalarizing a narrow vector (like v4f16). Fixes #168992
179 lines
6.6 KiB
LLVM
179 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s --check-prefix=VECTOR
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;
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; Test conversions between different-sized float elements.
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; Test cases where both elements of a v2f64 are converted to f16s.
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define void @f1(<2 x double> %val, ptr %ptr) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -176
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; CHECK-NEXT: .cfi_def_cfa_offset 336
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; CHECK-NEXT: std %f8, 168(%r15) # 8-byte Spill
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; CHECK-NEXT: std %f9, 160(%r15) # 8-byte Spill
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; CHECK-NEXT: .cfi_offset %f8, -168
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; CHECK-NEXT: .cfi_offset %f9, -176
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; CHECK-NEXT: lgr %r13, %r2
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; CHECK-NEXT: ldr %f8, %f2
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; CHECK-NEXT: brasl %r14, __truncdfhf2@PLT
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; CHECK-NEXT: ler %f9, %f0
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; CHECK-NEXT: ldr %f0, %f8
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; CHECK-NEXT: brasl %r14, __truncdfhf2@PLT
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; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d
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; CHECK-NEXT: lgdr %r0, %f0
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 2(%r13)
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; CHECK-NEXT: lgdr %r0, %f9
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 0(%r13)
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; CHECK-NEXT: ld %f8, 168(%r15) # 8-byte Reload
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; CHECK-NEXT: ld %f9, 160(%r15) # 8-byte Reload
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; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f1:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
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; VECTOR-NEXT: .cfi_offset %r13, -56
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; VECTOR-NEXT: .cfi_offset %r14, -48
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; VECTOR-NEXT: .cfi_offset %r15, -40
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; VECTOR-NEXT: aghi %r15, -184
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; VECTOR-NEXT: .cfi_def_cfa_offset 344
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; VECTOR-NEXT: std %f8, 176(%r15) # 8-byte Spill
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; VECTOR-NEXT: .cfi_offset %f8, -168
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; VECTOR-NEXT: lgr %r13, %r2
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; VECTOR-NEXT: vst %v24, 160(%r15), 3 # 16-byte Spill
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; VECTOR-NEXT: vrepg %v0, %v24, 1
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; VECTOR-NEXT: # kill: def $f0d killed $f0d killed $v0
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; VECTOR-NEXT: brasl %r14, __truncdfhf2@PLT
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; VECTOR-NEXT: ldr %f8, %f0
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; VECTOR-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
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; VECTOR-NEXT: # kill: def $f0d killed $f0d killed $v0
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; VECTOR-NEXT: brasl %r14, __truncdfhf2@PLT
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; VECTOR-NEXT: vsteh %v8, 2(%r13), 0
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; VECTOR-NEXT: ld %f8, 176(%r15) # 8-byte Reload
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; VECTOR-NEXT: vsteh %v0, 0(%r13), 0
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; VECTOR-NEXT: lmg %r13, %r15, 288(%r15)
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; VECTOR-NEXT: br %r14
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%res = fptrunc <2 x double> %val to <2 x half>
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store <2 x half> %res, ptr %ptr
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ret void
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}
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; Test conversion of an f64 in a vector register to an f16.
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define half @f2(<2 x double> %vec) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: brasl %r14, __truncdfhf2@PLT
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; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f2:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
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; VECTOR-NEXT: .cfi_offset %r14, -48
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; VECTOR-NEXT: .cfi_offset %r15, -40
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; VECTOR-NEXT: aghi %r15, -160
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; VECTOR-NEXT: .cfi_def_cfa_offset 320
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; VECTOR-NEXT: vlr %v0, %v24
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; VECTOR-NEXT: # kill: def $f0d killed $f0d killed $v0
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; VECTOR-NEXT: brasl %r14, __truncdfhf2@PLT
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; VECTOR-NEXT: lmg %r14, %r15, 272(%r15)
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; VECTOR-NEXT: br %r14
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%scalar = extractelement <2 x double> %vec, i32 0
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%ret = fptrunc double %scalar to half
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ret half %ret
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}
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; Test cases where even elements of a v4f16 are converted to f64s.
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define <2 x double> @f3(<4 x half> %vec) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -176
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; CHECK-NEXT: .cfi_def_cfa_offset 336
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; CHECK-NEXT: std %f8, 168(%r15) # 8-byte Spill
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; CHECK-NEXT: std %f9, 160(%r15) # 8-byte Spill
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; CHECK-NEXT: .cfi_offset %f8, -168
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; CHECK-NEXT: .cfi_offset %f9, -176
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; CHECK-NEXT: ler %f8, %f4
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; CHECK-NEXT: brasl %r14, __extendhfdf2@PLT
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; CHECK-NEXT: ldr %f9, %f0
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; CHECK-NEXT: ler %f0, %f8
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; CHECK-NEXT: brasl %r14, __extendhfdf2@PLT
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; CHECK-NEXT: ldr %f2, %f0
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; CHECK-NEXT: ldr %f0, %f9
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; CHECK-NEXT: ld %f8, 168(%r15) # 8-byte Reload
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; CHECK-NEXT: ld %f9, 160(%r15) # 8-byte Reload
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; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f3:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
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; VECTOR-NEXT: .cfi_offset %r14, -48
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; VECTOR-NEXT: .cfi_offset %r15, -40
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; VECTOR-NEXT: aghi %r15, -192
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; VECTOR-NEXT: .cfi_def_cfa_offset 352
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; VECTOR-NEXT: vreph %v1, %v24, 2
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; VECTOR-NEXT: vlr %v0, %v24
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; VECTOR-NEXT: vst %v1, 176(%r15), 3 # 16-byte Spill
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; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
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; VECTOR-NEXT: brasl %r14, __extendhfdf2@PLT
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; VECTOR-NEXT: # kill: def $f0d killed $f0d def $v0
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; VECTOR-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
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; VECTOR-NEXT: vl %v0, 176(%r15), 3 # 16-byte Reload
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; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
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; VECTOR-NEXT: brasl %r14, __extendhfdf2@PLT
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; VECTOR-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
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; VECTOR-NEXT: # kill: def $f0d killed $f0d def $v0
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; VECTOR-NEXT: vmrhg %v24, %v1, %v0
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; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
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; VECTOR-NEXT: br %r14
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%shuffle = shufflevector <4 x half> %vec, <4 x half> %vec, <2 x i32> <i32 0, i32 2>
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%res = fpext <2 x half> %shuffle to <2 x double>
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ret <2 x double> %res
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}
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; Test conversion of an f16 in a vector register to an f32, constant element index.
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define float @f4(<4 x half> %vec) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f4:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
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; VECTOR-NEXT: .cfi_offset %r14, -48
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; VECTOR-NEXT: .cfi_offset %r15, -40
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; VECTOR-NEXT: aghi %r15, -160
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; VECTOR-NEXT: .cfi_def_cfa_offset 320
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; VECTOR-NEXT: vlr %v0, %v24
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; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
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; VECTOR-NEXT: brasl %r14, __extendhfsf2@PLT
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; VECTOR-NEXT: lmg %r14, %r15, 272(%r15)
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; VECTOR-NEXT: br %r14
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%scalar = extractelement <4 x half> %vec, i32 0
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%ret = fpext half %scalar to float
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ret float %ret
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}
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