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llvm-project/llvm/test/CodeGen/SystemZ/args-22.ll
Jonas Paulsson 0b252daf64 [SystemZ] Handle IR struct arguments correctly. (#169583) 
- The size of the stack slot was previously computed in LowerCall() by using
  the original type, but that didn't work for a struct. Compute the size
  by looking at the VT of each part and the number of them instead.

- All the members of a struct have the same OrigArgIndex, so it doesn't work
  to assume that following parts belong to a split argument until another
  OrigArgIndex is encountered. Use the isSplit() and isSplitEnd() flags
  instead.

- Detect any scalar integer argumet >64 bits in CanLowerReturn() instead of
  just i128, in order to let all of them be passed on stack.
  
Fixes #168460
2025-12-04 13:14:31 -06:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s --check-prefix=VECTOR
;
; Test passing IR struct arguments, which do not adhere to the SystemZ ABI but are
; split up with each element passed like a separate argument.
@Fnptr = external global ptr
@Src = external global ptr
@Dst = external global ptr
%Ty0 = type {i128}
define void @arg0(%Ty0 %A) {
; CHECK-LABEL: arg0:
; CHECK: # %bb.0:
; CHECK-NEXT: lg %r0, 8(%r2)
; CHECK-NEXT: lgrl %r1, Dst@GOT
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stg %r0, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg0:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v0, 0(%r2), 3
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: vst %v0, 0(%r1), 3
; VECTOR-NEXT: br %r14
store %Ty0 %A, ptr @Dst
ret void
}
define void @call0() {
; CHECK-LABEL: call0:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -176
; CHECK-NEXT: .cfi_def_cfa_offset 336
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r0, 8(%r1)
; CHECK-NEXT: lg %r1, 0(%r1)
; CHECK-NEXT: stg %r0, 168(%r15)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: stg %r1, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call0:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -176
; VECTOR-NEXT: .cfi_def_cfa_offset 336
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: vl %v0, 0(%r1), 3
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: vst %v0, 160(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r14, %r15, 288(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty0, ptr @Src
call void @Fnptr(%Ty0 %L)
ret void
}
define %Ty0 @ret0() {
; CHECK-LABEL: ret0:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -176
; CHECK-NEXT: .cfi_def_cfa_offset 336
; CHECK-NEXT: lgr %r13, %r2
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lg %r0, 168(%r15)
; CHECK-NEXT: lg %r1, 160(%r15)
; CHECK-NEXT: stg %r0, 8(%r13)
; CHECK-NEXT: stg %r1, 0(%r13)
; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: ret0:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
; VECTOR-NEXT: .cfi_offset %r13, -56
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -176
; VECTOR-NEXT: .cfi_def_cfa_offset 336
; VECTOR-NEXT: lgr %r13, %r2
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: vl %v0, 160(%r15), 3
; VECTOR-NEXT: vst %v0, 0(%r13), 3
; VECTOR-NEXT: lmg %r13, %r15, 280(%r15)
; VECTOR-NEXT: br %r14
%C = call %Ty0 @Fnptr()
ret %Ty0 %C
}
%Ty1 = type {i72}
define void @arg1(%Ty1 %A) {
; CHECK-LABEL: arg1:
; CHECK: # %bb.0:
; CHECK-NEXT: lg %r0, 8(%r2)
; CHECK-NEXT: lgrl %r1, Dst@GOT
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stc %r0, 8(%r1)
; CHECK-NEXT: sllg %r2, %r2, 56
; CHECK-NEXT: rosbg %r2, %r0, 8, 63, 56
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg1:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v0, 0(%r2), 3
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: vrepib %v1, 8
; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
; VECTOR-NEXT: vsrlb %v0, %v0, %v1
; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty1 %A, ptr @Dst
ret void
}
define void @call1() {
; CHECK-LABEL: call1:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -176
; CHECK-NEXT: .cfi_def_cfa_offset 336
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r0, 0(%r1)
; CHECK-NEXT: sllg %r2, %r0, 8
; CHECK-NEXT: ic %r2, 8(%r1)
; CHECK-NEXT: srlg %r0, %r0, 56
; CHECK-NEXT: stg %r2, 168(%r15)
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: stg %r0, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call1:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -176
; VECTOR-NEXT: .cfi_def_cfa_offset 336
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vleb %v0, 8(%r1), 15
; VECTOR-NEXT: vlrepg %v1, 0(%r1)
; VECTOR-NEXT: vrepib %v2, 8
; VECTOR-NEXT: vslb %v1, %v1, %v2
; VECTOR-NEXT: vo %v0, %v0, %v1
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: vst %v0, 160(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r14, %r15, 288(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty1, ptr @Src
call void @Fnptr(%Ty1 %L)
ret void
}
define %Ty1 @ret1() {
; CHECK-LABEL: ret1:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -176
; CHECK-NEXT: .cfi_def_cfa_offset 336
; CHECK-NEXT: lgr %r13, %r2
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lg %r0, 160(%r15)
; CHECK-NEXT: llgc %r1, 168(%r15)
; CHECK-NEXT: stg %r0, 0(%r13)
; CHECK-NEXT: stc %r1, 8(%r13)
; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: ret1:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
; VECTOR-NEXT: .cfi_offset %r13, -56
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -176
; VECTOR-NEXT: .cfi_def_cfa_offset 336
; VECTOR-NEXT: lgr %r13, %r2
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vleb %v0, 168(%r15), 15
; VECTOR-NEXT: vlrepg %v1, 160(%r15)
; VECTOR-NEXT: vsteg %v1, 0(%r13), 1
; VECTOR-NEXT: vsteb %v0, 8(%r13), 15
; VECTOR-NEXT: lmg %r13, %r15, 280(%r15)
; VECTOR-NEXT: br %r14
%C = call %Ty1 @Fnptr()
ret %Ty1 %C
}
%Ty2 = type {i128, i128}
define void @arg2(%Ty2 %A) {
; CHECK-LABEL: arg2:
; CHECK: # %bb.0:
; CHECK-NEXT: lg %r0, 8(%r3)
; CHECK-NEXT: lgrl %r1, Dst@GOT
; CHECK-NEXT: lg %r3, 0(%r3)
; CHECK-NEXT: lg %r4, 8(%r2)
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stg %r0, 24(%r1)
; CHECK-NEXT: stg %r3, 16(%r1)
; CHECK-NEXT: stg %r4, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg2:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v0, 0(%r2), 3
; VECTOR-NEXT: vl %v1, 0(%r3), 3
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: vst %v1, 16(%r1), 3
; VECTOR-NEXT: vst %v0, 0(%r1), 3
; VECTOR-NEXT: br %r14
store %Ty2 %A, ptr @Dst
ret void
}
define void @call2() {
; CHECK-LABEL: call2:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r0, 24(%r1)
; CHECK-NEXT: lg %r2, 16(%r1)
; CHECK-NEXT: lg %r3, 8(%r1)
; CHECK-NEXT: lg %r1, 0(%r1)
; CHECK-NEXT: stg %r0, 168(%r15)
; CHECK-NEXT: stg %r2, 160(%r15)
; CHECK-NEXT: stg %r3, 184(%r15)
; CHECK-NEXT: la %r2, 176(%r15)
; CHECK-NEXT: la %r3, 160(%r15)
; CHECK-NEXT: stg %r1, 176(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call2:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: vl %v0, 0(%r1), 3
; VECTOR-NEXT: vl %v1, 16(%r1), 3
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
; VECTOR-NEXT: vst %v1, 160(%r15), 3
; VECTOR-NEXT: vst %v0, 176(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty2, ptr @Src
call void @Fnptr(%Ty2 %L)
ret void
}
define %Ty2 @ret2() {
; CHECK-LABEL: ret2:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgr %r13, %r2
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lg %r0, 176(%r15)
; CHECK-NEXT: lg %r1, 184(%r15)
; CHECK-NEXT: lg %r2, 160(%r15)
; CHECK-NEXT: lg %r3, 168(%r15)
; CHECK-NEXT: stg %r0, 16(%r13)
; CHECK-NEXT: stg %r1, 24(%r13)
; CHECK-NEXT: stg %r2, 0(%r13)
; CHECK-NEXT: stg %r3, 8(%r13)
; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: ret2:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
; VECTOR-NEXT: .cfi_offset %r13, -56
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgr %r13, %r2
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: vl %v0, 160(%r15), 3
; VECTOR-NEXT: vl %v1, 176(%r15), 3
; VECTOR-NEXT: vst %v1, 16(%r13), 3
; VECTOR-NEXT: vst %v0, 0(%r13), 3
; VECTOR-NEXT: lmg %r13, %r15, 296(%r15)
; VECTOR-NEXT: br %r14
%C = call %Ty2 @Fnptr()
ret %Ty2 %C
}
%Ty3 = type {i72, i128}
define void @arg3(%Ty3 %A) {
; CHECK-LABEL: arg3:
; CHECK: # %bb.0:
; CHECK-NEXT: lg %r0, 8(%r3)
; CHECK-NEXT: lgrl %r1, Dst@GOT
; CHECK-NEXT: lg %r3, 0(%r3)
; CHECK-NEXT: lg %r4, 8(%r2)
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stg %r0, 24(%r1)
; CHECK-NEXT: stg %r3, 16(%r1)
; CHECK-NEXT: stc %r4, 8(%r1)
; CHECK-NEXT: sllg %r0, %r2, 56
; CHECK-NEXT: rosbg %r0, %r4, 8, 63, 56
; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg3:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v0, 0(%r3), 3
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: vl %v1, 0(%r2), 3
; VECTOR-NEXT: vsteb %v1, 8(%r1), 15
; VECTOR-NEXT: vst %v0, 16(%r1), 3
; VECTOR-NEXT: vrepib %v0, 8
; VECTOR-NEXT: vsrlb %v0, %v1, %v0
; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty3 %A, ptr @Dst
ret void
}
define void @call3() {
; CHECK-LABEL: call3:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r0, 0(%r1)
; CHECK-NEXT: sllg %r2, %r0, 8
; CHECK-NEXT: lg %r3, 24(%r1)
; CHECK-NEXT: lg %r4, 16(%r1)
; CHECK-NEXT: ic %r2, 8(%r1)
; CHECK-NEXT: srlg %r0, %r0, 56
; CHECK-NEXT: stg %r3, 168(%r15)
; CHECK-NEXT: stg %r4, 160(%r15)
; CHECK-NEXT: stg %r2, 184(%r15)
; CHECK-NEXT: la %r2, 176(%r15)
; CHECK-NEXT: la %r3, 160(%r15)
; CHECK-NEXT: stg %r0, 176(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call3:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vleb %v0, 8(%r1), 15
; VECTOR-NEXT: vlrepg %v1, 0(%r1)
; VECTOR-NEXT: vrepib %v2, 8
; VECTOR-NEXT: vslb %v1, %v1, %v2
; VECTOR-NEXT: vo %v0, %v0, %v1
; VECTOR-NEXT: vl %v1, 16(%r1), 3
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
; VECTOR-NEXT: vst %v1, 160(%r15), 3
; VECTOR-NEXT: vst %v0, 176(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty3, ptr @Src
call void @Fnptr(%Ty3 %L)
ret void
}
define %Ty3 @ret3() {
; CHECK-LABEL: ret3:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgr %r13, %r2
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lg %r0, 176(%r15)
; CHECK-NEXT: lg %r1, 184(%r15)
; CHECK-NEXT: lg %r2, 160(%r15)
; CHECK-NEXT: llgc %r3, 168(%r15)
; CHECK-NEXT: stg %r0, 16(%r13)
; CHECK-NEXT: stg %r1, 24(%r13)
; CHECK-NEXT: stg %r2, 0(%r13)
; CHECK-NEXT: stc %r3, 8(%r13)
; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: ret3:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
; VECTOR-NEXT: .cfi_offset %r13, -56
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgr %r13, %r2
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vleb %v0, 168(%r15), 15
; VECTOR-NEXT: vlrepg %v1, 160(%r15)
; VECTOR-NEXT: vl %v2, 176(%r15), 3
; VECTOR-NEXT: vst %v2, 16(%r13), 3
; VECTOR-NEXT: vsteg %v1, 0(%r13), 1
; VECTOR-NEXT: vsteb %v0, 8(%r13), 15
; VECTOR-NEXT: lmg %r13, %r15, 296(%r15)
; VECTOR-NEXT: br %r14
%C = call %Ty3 @Fnptr()
ret %Ty3 %C
}
%Ty4 = type {float, i8, i16, i32, i64, i128, i8}
define void @arg4(%Ty4 %A) {
; CHECK-LABEL: arg4:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: l %r0, 164(%r15)
; CHECK-NEXT: lgrl %r1, Dst@GOT
; CHECK-NEXT: lg %r14, 0(%r6)
; CHECK-NEXT: lg %r13, 8(%r6)
; CHECK-NEXT: stc %r0, 40(%r1)
; CHECK-NEXT: stg %r5, 16(%r1)
; CHECK-NEXT: st %r4, 8(%r1)
; CHECK-NEXT: sth %r3, 6(%r1)
; CHECK-NEXT: stc %r2, 4(%r1)
; CHECK-NEXT: ste %f0, 0(%r1)
; CHECK-NEXT: stg %r13, 32(%r1)
; CHECK-NEXT: stg %r14, 24(%r1)
; CHECK-NEXT: lmg %r13, %r15, 104(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg4:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v1, 0(%r6), 3
; VECTOR-NEXT: l %r0, 164(%r15)
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: stc %r0, 40(%r1)
; VECTOR-NEXT: stg %r5, 16(%r1)
; VECTOR-NEXT: st %r4, 8(%r1)
; VECTOR-NEXT: sth %r3, 6(%r1)
; VECTOR-NEXT: stc %r2, 4(%r1)
; VECTOR-NEXT: ste %f0, 0(%r1)
; VECTOR-NEXT: vst %v1, 24(%r1), 3
; VECTOR-NEXT: br %r14
store %Ty4 %A, ptr @Dst
ret void
}
define void @call4() {
; CHECK-LABEL: call4:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
; CHECK-NEXT: .cfi_offset %r6, -112
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -184
; CHECK-NEXT: .cfi_def_cfa_offset 344
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r5, 16(%r1)
; CHECK-NEXT: l %r4, 8(%r1)
; CHECK-NEXT: le %f0, 0(%r1)
; CHECK-NEXT: lg %r0, 24(%r1)
; CHECK-NEXT: lb %r14, 40(%r1)
; CHECK-NEXT: lg %r13, 32(%r1)
; CHECK-NEXT: lh %r3, 6(%r1)
; CHECK-NEXT: lb %r2, 4(%r1)
; CHECK-NEXT: st %r14, 164(%r15)
; CHECK-NEXT: stg %r13, 176(%r15)
; CHECK-NEXT: la %r6, 168(%r15)
; CHECK-NEXT: stg %r0, 168(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r6, %r15, 232(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call4:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r6, %r15, 48(%r15)
; VECTOR-NEXT: .cfi_offset %r6, -112
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -184
; VECTOR-NEXT: .cfi_def_cfa_offset 344
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: lh %r3, 6(%r1)
; VECTOR-NEXT: lb %r2, 4(%r1)
; VECTOR-NEXT: lb %r0, 40(%r1)
; VECTOR-NEXT: lg %r5, 16(%r1)
; VECTOR-NEXT: l %r4, 8(%r1)
; VECTOR-NEXT: lde %f0, 0(%r1)
; VECTOR-NEXT: vl %v1, 24(%r1), 3
; VECTOR-NEXT: la %r6, 168(%r15)
; VECTOR-NEXT: st %r0, 164(%r15)
; VECTOR-NEXT: vst %v1, 168(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r6, %r15, 232(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty4, ptr @Src
call void @Fnptr(%Ty4 %L)
ret void
}
define %Ty4 @ret4() {
; CHECK-LABEL: ret4:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -208
; CHECK-NEXT: .cfi_def_cfa_offset 368
; CHECK-NEXT: lgr %r13, %r2
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lb %r0, 164(%r15)
; CHECK-NEXT: lh %r1, 166(%r15)
; CHECK-NEXT: lg %r2, 192(%r15)
; CHECK-NEXT: lg %r3, 184(%r15)
; CHECK-NEXT: le %f0, 160(%r15)
; CHECK-NEXT: l %r4, 168(%r15)
; CHECK-NEXT: lg %r5, 176(%r15)
; CHECK-NEXT: lb %r14, 200(%r15)
; CHECK-NEXT: ste %f0, 0(%r13)
; CHECK-NEXT: st %r4, 8(%r13)
; CHECK-NEXT: stg %r5, 16(%r13)
; CHECK-NEXT: stc %r14, 40(%r13)
; CHECK-NEXT: stg %r3, 24(%r13)
; CHECK-NEXT: stg %r2, 32(%r13)
; CHECK-NEXT: sth %r1, 6(%r13)
; CHECK-NEXT: stc %r0, 4(%r13)
; CHECK-NEXT: lmg %r13, %r15, 312(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: ret4:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
; VECTOR-NEXT: .cfi_offset %r13, -56
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -208
; VECTOR-NEXT: .cfi_def_cfa_offset 368
; VECTOR-NEXT: lgr %r13, %r2
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lb %r0, 164(%r15)
; VECTOR-NEXT: lh %r1, 166(%r15)
; VECTOR-NEXT: lb %r4, 200(%r15)
; VECTOR-NEXT: lde %f0, 160(%r15)
; VECTOR-NEXT: l %r2, 168(%r15)
; VECTOR-NEXT: lg %r3, 176(%r15)
; VECTOR-NEXT: vl %v1, 184(%r15), 3
; VECTOR-NEXT: stc %r4, 40(%r13)
; VECTOR-NEXT: vst %v1, 24(%r13), 3
; VECTOR-NEXT: stg %r3, 16(%r13)
; VECTOR-NEXT: st %r2, 8(%r13)
; VECTOR-NEXT: sth %r1, 6(%r13)
; VECTOR-NEXT: stc %r0, 4(%r13)
; VECTOR-NEXT: ste %f0, 0(%r13)
; VECTOR-NEXT: lmg %r13, %r15, 312(%r15)
; VECTOR-NEXT: br %r14
%C = call %Ty4 @Fnptr()
ret %Ty4 %C
}
%Ty5 = type [4 x i128]
define void @arg5(%Ty5 %A) {
; CHECK-LABEL: arg5:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
; CHECK-NEXT: .cfi_offset %r12, -64
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: lg %r0, 0(%r2)
; CHECK-NEXT: lg %r1, 8(%r2)
; CHECK-NEXT: lg %r2, 0(%r3)
; CHECK-NEXT: lg %r3, 8(%r3)
; CHECK-NEXT: lg %r14, 8(%r5)
; CHECK-NEXT: lgrl %r13, Dst@GOT
; CHECK-NEXT: lg %r5, 0(%r5)
; CHECK-NEXT: lg %r12, 8(%r4)
; CHECK-NEXT: lg %r4, 0(%r4)
; CHECK-NEXT: stg %r14, 56(%r13)
; CHECK-NEXT: stg %r5, 48(%r13)
; CHECK-NEXT: stg %r12, 40(%r13)
; CHECK-NEXT: stg %r4, 32(%r13)
; CHECK-NEXT: stg %r3, 24(%r13)
; CHECK-NEXT: stg %r2, 16(%r13)
; CHECK-NEXT: stg %r1, 8(%r13)
; CHECK-NEXT: stg %r0, 0(%r13)
; CHECK-NEXT: lmg %r12, %r15, 96(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg5:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v0, 0(%r2), 3
; VECTOR-NEXT: vl %v1, 0(%r3), 3
; VECTOR-NEXT: vl %v2, 0(%r4), 3
; VECTOR-NEXT: vl %v3, 0(%r5), 3
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: vst %v3, 48(%r1), 3
; VECTOR-NEXT: vst %v2, 32(%r1), 3
; VECTOR-NEXT: vst %v1, 16(%r1), 3
; VECTOR-NEXT: vst %v0, 0(%r1), 3
; VECTOR-NEXT: br %r14
store %Ty5 %A, ptr @Dst
ret void
}
define void @call5() {
; CHECK-LABEL: call5:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -224
; CHECK-NEXT: .cfi_def_cfa_offset 384
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r0, 0(%r1)
; CHECK-NEXT: lg %r2, 8(%r1)
; CHECK-NEXT: lg %r3, 16(%r1)
; CHECK-NEXT: lg %r4, 24(%r1)
; CHECK-NEXT: lg %r5, 56(%r1)
; CHECK-NEXT: lg %r14, 48(%r1)
; CHECK-NEXT: lg %r13, 40(%r1)
; CHECK-NEXT: lg %r1, 32(%r1)
; CHECK-NEXT: stg %r5, 168(%r15)
; CHECK-NEXT: stg %r14, 160(%r15)
; CHECK-NEXT: stg %r13, 184(%r15)
; CHECK-NEXT: stg %r1, 176(%r15)
; CHECK-NEXT: stg %r4, 200(%r15)
; CHECK-NEXT: stg %r3, 192(%r15)
; CHECK-NEXT: stg %r2, 216(%r15)
; CHECK-NEXT: la %r2, 208(%r15)
; CHECK-NEXT: la %r3, 192(%r15)
; CHECK-NEXT: la %r4, 176(%r15)
; CHECK-NEXT: la %r5, 160(%r15)
; CHECK-NEXT: stg %r0, 208(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r13, %r15, 328(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call5:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -224
; VECTOR-NEXT: .cfi_def_cfa_offset 384
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: vl %v0, 0(%r1), 3
; VECTOR-NEXT: vl %v1, 16(%r1), 3
; VECTOR-NEXT: vl %v2, 32(%r1), 3
; VECTOR-NEXT: vl %v3, 48(%r1), 3
; VECTOR-NEXT: la %r2, 208(%r15)
; VECTOR-NEXT: la %r3, 192(%r15)
; VECTOR-NEXT: la %r4, 176(%r15)
; VECTOR-NEXT: la %r5, 160(%r15)
; VECTOR-NEXT: vst %v3, 160(%r15), 3
; VECTOR-NEXT: vst %v2, 176(%r15), 3
; VECTOR-NEXT: vst %v1, 192(%r15), 3
; VECTOR-NEXT: vst %v0, 208(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r14, %r15, 336(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty5, ptr @Src
call void @Fnptr(%Ty5 %L)
ret void
}
define %Ty5 @ret5() {
; CHECK-LABEL: ret5:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
; CHECK-NEXT: .cfi_offset %r12, -64
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -224
; CHECK-NEXT: .cfi_def_cfa_offset 384
; CHECK-NEXT: lgr %r13, %r2
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lg %r0, 168(%r15)
; CHECK-NEXT: lg %r1, 160(%r15)
; CHECK-NEXT: lg %r2, 184(%r15)
; CHECK-NEXT: lg %r3, 176(%r15)
; CHECK-NEXT: lg %r4, 208(%r15)
; CHECK-NEXT: lg %r5, 216(%r15)
; CHECK-NEXT: lg %r14, 192(%r15)
; CHECK-NEXT: lg %r12, 200(%r15)
; CHECK-NEXT: stg %r4, 48(%r13)
; CHECK-NEXT: stg %r5, 56(%r13)
; CHECK-NEXT: stg %r14, 32(%r13)
; CHECK-NEXT: stg %r12, 40(%r13)
; CHECK-NEXT: stg %r3, 16(%r13)
; CHECK-NEXT: stg %r2, 24(%r13)
; CHECK-NEXT: stg %r1, 0(%r13)
; CHECK-NEXT: stg %r0, 8(%r13)
; CHECK-NEXT: lmg %r12, %r15, 320(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: ret5:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
; VECTOR-NEXT: .cfi_offset %r13, -56
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -224
; VECTOR-NEXT: .cfi_def_cfa_offset 384
; VECTOR-NEXT: lgr %r13, %r2
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: vl %v0, 160(%r15), 3
; VECTOR-NEXT: vl %v1, 176(%r15), 3
; VECTOR-NEXT: vl %v2, 192(%r15), 3
; VECTOR-NEXT: vl %v3, 208(%r15), 3
; VECTOR-NEXT: vst %v3, 48(%r13), 3
; VECTOR-NEXT: vst %v2, 32(%r13), 3
; VECTOR-NEXT: vst %v1, 16(%r13), 3
; VECTOR-NEXT: vst %v0, 0(%r13), 3
; VECTOR-NEXT: lmg %r13, %r15, 328(%r15)
; VECTOR-NEXT: br %r14
%C = call %Ty5 @Fnptr()
ret %Ty5 %C
}
%Ty6 = type [2 x i72]
define void @arg6(%Ty6 %A) {
; CHECK-LABEL: arg6:
; CHECK: # %bb.0:
; CHECK-NEXT: lg %r0, 8(%r3)
; CHECK-NEXT: lgrl %r1, Dst@GOT
; CHECK-NEXT: lg %r4, 8(%r2)
; CHECK-NEXT: lg %r3, 0(%r3)
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: stc %r0, 24(%r1)
; CHECK-NEXT: stc %r4, 8(%r1)
; CHECK-NEXT: sllg %r3, %r3, 56
; CHECK-NEXT: rosbg %r3, %r0, 8, 63, 56
; CHECK-NEXT: stg %r3, 16(%r1)
; CHECK-NEXT: sllg %r0, %r2, 56
; CHECK-NEXT: rosbg %r0, %r4, 8, 63, 56
; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg6:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v0, 0(%r2), 3
; VECTOR-NEXT: vl %v1, 0(%r3), 3
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: vsteb %v1, 24(%r1), 15
; VECTOR-NEXT: vrepib %v2, 8
; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
; VECTOR-NEXT: vsrlb %v1, %v1, %v2
; VECTOR-NEXT: vsrlb %v0, %v0, %v2
; VECTOR-NEXT: vsteg %v1, 16(%r1), 1
; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty6 %A, ptr @Dst
ret void
}
define void @call6() {
; CHECK-LABEL: call6:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r0, 0(%r1)
; CHECK-NEXT: lg %r2, 16(%r1)
; CHECK-NEXT: sllg %r3, %r0, 8
; CHECK-NEXT: sllg %r4, %r2, 8
; CHECK-NEXT: ic %r4, 24(%r1)
; CHECK-NEXT: ic %r3, 8(%r1)
; CHECK-NEXT: srlg %r0, %r0, 56
; CHECK-NEXT: srlg %r1, %r2, 56
; CHECK-NEXT: stg %r4, 168(%r15)
; CHECK-NEXT: stg %r1, 160(%r15)
; CHECK-NEXT: stg %r3, 184(%r15)
; CHECK-NEXT: la %r2, 176(%r15)
; CHECK-NEXT: la %r3, 160(%r15)
; CHECK-NEXT: stg %r0, 176(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call6:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: vgbm %v1, 0
; VECTOR-NEXT: vleb %v1, 8(%r1), 15
; VECTOR-NEXT: vlrepg %v2, 0(%r1)
; VECTOR-NEXT: vrepib %v3, 8
; VECTOR-NEXT: vslb %v2, %v2, %v3
; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vo %v1, %v1, %v2
; VECTOR-NEXT: vleb %v0, 24(%r1), 15
; VECTOR-NEXT: vlrepg %v2, 16(%r1)
; VECTOR-NEXT: vslb %v2, %v2, %v3
; VECTOR-NEXT: vo %v0, %v0, %v2
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
; VECTOR-NEXT: vst %v0, 160(%r15), 3
; VECTOR-NEXT: vst %v1, 176(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty6, ptr @Src
call void @Fnptr(%Ty6 %L)
ret void
}
define %Ty6 @ret6() {
; CHECK-LABEL: ret6:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
; CHECK-NEXT: .cfi_offset %r13, -56
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgr %r13, %r2
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lg %r0, 176(%r15)
; CHECK-NEXT: llgc %r1, 184(%r15)
; CHECK-NEXT: lg %r2, 160(%r15)
; CHECK-NEXT: llgc %r3, 168(%r15)
; CHECK-NEXT: stg %r0, 16(%r13)
; CHECK-NEXT: stc %r1, 24(%r13)
; CHECK-NEXT: stg %r2, 0(%r13)
; CHECK-NEXT: stc %r3, 8(%r13)
; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: ret6:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r13, %r15, 104(%r15)
; VECTOR-NEXT: .cfi_offset %r13, -56
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgr %r13, %r2
; VECTOR-NEXT: la %r2, 160(%r15)
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vgbm %v1, 0
; VECTOR-NEXT: vleb %v1, 168(%r15), 15
; VECTOR-NEXT: vleb %v0, 184(%r15), 15
; VECTOR-NEXT: vlrepg %v2, 160(%r15)
; VECTOR-NEXT: vlrepg %v3, 176(%r15)
; VECTOR-NEXT: vsteg %v3, 16(%r13), 1
; VECTOR-NEXT: vsteb %v0, 24(%r13), 15
; VECTOR-NEXT: vsteg %v2, 0(%r13), 1
; VECTOR-NEXT: vsteb %v1, 8(%r13), 15
; VECTOR-NEXT: lmg %r13, %r15, 296(%r15)
; VECTOR-NEXT: br %r14
%C = call %Ty6 @Fnptr()
ret %Ty6 %C
}
%Ty7 = type {i128}
define void @arg7(%Ty7 %A, %Ty7 %B) {
; CHECK-LABEL: arg7:
; CHECK: # %bb.0:
; CHECK-NEXT: lg %r0, 8(%r2)
; CHECK-NEXT: lgrl %r1, Dst@GOT
; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: lg %r4, 8(%r3)
; CHECK-NEXT: lg %r3, 0(%r3)
; CHECK-NEXT: stg %r0, 8(%r1)
; CHECK-NEXT: stg %r2, 0(%r1)
; CHECK-NEXT: stg %r4, 24(%r1)
; CHECK-NEXT: stg %r3, 16(%r1)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: arg7:
; VECTOR: # %bb.0:
; VECTOR-NEXT: vl %v0, 0(%r3), 3
; VECTOR-NEXT: vl %v1, 0(%r2), 3
; VECTOR-NEXT: lgrl %r1, Dst@GOT
; VECTOR-NEXT: vst %v1, 0(%r1), 3
; VECTOR-NEXT: vst %v0, 16(%r1), 3
; VECTOR-NEXT: br %r14
store %Ty7 %A, ptr @Dst
%D2 = getelementptr %Ty7, ptr @Dst, i32 1
store %Ty7 %B, ptr %D2
ret void
}
define void @call7() {
; CHECK-LABEL: call7:
; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, Src@GOT
; CHECK-NEXT: lg %r0, 24(%r1)
; CHECK-NEXT: lg %r2, 16(%r1)
; CHECK-NEXT: lg %r3, 8(%r1)
; CHECK-NEXT: lg %r1, 0(%r1)
; CHECK-NEXT: stg %r0, 168(%r15)
; CHECK-NEXT: stg %r2, 160(%r15)
; CHECK-NEXT: stg %r3, 184(%r15)
; CHECK-NEXT: la %r2, 176(%r15)
; CHECK-NEXT: la %r3, 160(%r15)
; CHECK-NEXT: stg %r1, 176(%r15)
; CHECK-NEXT: brasl %r14, Fnptr@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
;
; VECTOR-LABEL: call7:
; VECTOR: # %bb.0:
; VECTOR-NEXT: stmg %r14, %r15, 112(%r15)
; VECTOR-NEXT: .cfi_offset %r14, -48
; VECTOR-NEXT: .cfi_offset %r15, -40
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgrl %r1, Src@GOT
; VECTOR-NEXT: vl %v0, 0(%r1), 3
; VECTOR-NEXT: vl %v1, 16(%r1), 3
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
; VECTOR-NEXT: vst %v1, 160(%r15), 3
; VECTOR-NEXT: vst %v0, 176(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr@PLT
; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
; VECTOR-NEXT: br %r14
%L = load %Ty7, ptr @Src
%S2 = getelementptr %Ty7, ptr @Src, i32 1
%L2 = load %Ty7, ptr %S2
call void @Fnptr(%Ty7 %L, %Ty7 %L2)
ret void
}
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