0c0b0ea887
Early Niagara processors (T1-T3) lacks any branch predictor, yet they also have a pipeline long enough that the delay slot cannot cover for all of the branch latency. This means that branch instructions will stall the processor for a couple cycles, which makes them an expensive operation. Additionally, the high cost of branching means that it's still profitable to prefer conditional moves even when the conditional is predictable, so let LLVM know about both things. On SPARC T2, a pgbench test seem to show a modest, but pretty consistent speedup (up to around 3%).
81 lines
3.1 KiB
LLVM
81 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparc -mcpu=v9 | FileCheck --check-prefix=SPARC %s
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; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64 %s
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; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparc -mcpu=v9 -mattr=+no-predictor | FileCheck --check-prefix=SPARC-NO-PREDICTOR %s
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; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparcv9 -mattr=+no-predictor | FileCheck --check-prefix=SPARC64-NO-PREDICTOR %s
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;; Normally, highly predictable selects should be turned into branches.
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;; On the other hand, early Niagara processors should prefer conditional moves
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;; over branches even when it's predictable.
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define i32 @cdiv(i32 %cond, i32 %num) #0 {
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; SPARC-LABEL: cdiv:
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; SPARC: ! %bb.0: ! %entry
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; SPARC-NEXT: cmp %o0, 0
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; SPARC-NEXT: be %icc, .LBB0_2
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; SPARC-NEXT: mov %o1, %o0
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; SPARC-NEXT: ! %bb.1: ! %select.end
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; SPARC-NEXT: retl
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; SPARC-NEXT: nop
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; SPARC-NEXT: .LBB0_2: ! %select.true.sink
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; SPARC-NEXT: sethi 1398101, %o1
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; SPARC-NEXT: or %o1, 342, %o1
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; SPARC-NEXT: smul %o0, %o1, %o0
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; SPARC-NEXT: rd %y, %o0
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; SPARC-NEXT: srl %o0, 31, %o1
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; SPARC-NEXT: retl
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; SPARC-NEXT: add %o0, %o1, %o0
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;
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; SPARC64-LABEL: cdiv:
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; SPARC64: ! %bb.0: ! %entry
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; SPARC64-NEXT: cmp %o0, 0
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; SPARC64-NEXT: be %icc, .LBB0_2
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; SPARC64-NEXT: mov %o1, %o0
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; SPARC64-NEXT: ! %bb.1: ! %select.end
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; SPARC64-NEXT: retl
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; SPARC64-NEXT: nop
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; SPARC64-NEXT: .LBB0_2: ! %select.true.sink
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; SPARC64-NEXT: sra %o0, 0, %o0
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; SPARC64-NEXT: sethi 1398101, %o1
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; SPARC64-NEXT: or %o1, 342, %o1
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; SPARC64-NEXT: mulx %o0, %o1, %o0
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; SPARC64-NEXT: srlx %o0, 63, %o1
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; SPARC64-NEXT: srlx %o0, 32, %o0
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; SPARC64-NEXT: retl
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; SPARC64-NEXT: add %o0, %o1, %o0
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;
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; SPARC-NO-PREDICTOR-LABEL: cdiv:
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; SPARC-NO-PREDICTOR: ! %bb.0: ! %entry
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; SPARC-NO-PREDICTOR-NEXT: sethi 1398101, %o2
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; SPARC-NO-PREDICTOR-NEXT: or %o2, 342, %o2
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; SPARC-NO-PREDICTOR-NEXT: smul %o1, %o2, %o2
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; SPARC-NO-PREDICTOR-NEXT: rd %y, %o2
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; SPARC-NO-PREDICTOR-NEXT: srl %o2, 31, %o3
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; SPARC-NO-PREDICTOR-NEXT: add %o2, %o3, %o2
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; SPARC-NO-PREDICTOR-NEXT: cmp %o0, 0
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; SPARC-NO-PREDICTOR-NEXT: move %icc, %o2, %o1
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; SPARC-NO-PREDICTOR-NEXT: retl
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; SPARC-NO-PREDICTOR-NEXT: mov %o1, %o0
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;
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; SPARC64-NO-PREDICTOR-LABEL: cdiv:
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; SPARC64-NO-PREDICTOR: ! %bb.0: ! %entry
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; SPARC64-NO-PREDICTOR-NEXT: sra %o1, 0, %o2
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; SPARC64-NO-PREDICTOR-NEXT: sethi 1398101, %o3
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; SPARC64-NO-PREDICTOR-NEXT: or %o3, 342, %o3
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; SPARC64-NO-PREDICTOR-NEXT: mulx %o2, %o3, %o2
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; SPARC64-NO-PREDICTOR-NEXT: srlx %o2, 63, %o3
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; SPARC64-NO-PREDICTOR-NEXT: srlx %o2, 32, %o2
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; SPARC64-NO-PREDICTOR-NEXT: add %o2, %o3, %o2
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; SPARC64-NO-PREDICTOR-NEXT: cmp %o0, 0
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; SPARC64-NO-PREDICTOR-NEXT: move %icc, %o2, %o1
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; SPARC64-NO-PREDICTOR-NEXT: retl
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; SPARC64-NO-PREDICTOR-NEXT: mov %o1, %o0
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entry:
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%div = sdiv i32 %num, 3
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%cmp = icmp eq i32 %cond, 0
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%ret = select i1 %cmp, i32 %div, i32 %num
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ret i32 %ret
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}
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attributes #0 = { nounwind }
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