b3564b2f5d
IR should be a splat of 7 as this compares vector of elements with 7 (`vec[i]!=7`). Having `zeroinitializer` goes against this comparison. Co-authored-by: himadhith <himadhith.v@ibm.com>
75 lines
3.0 KiB
LLVM
75 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64LE
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc-ibm-aix \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_32
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; The current implementation is comparing vector of non-zeros in register v2 with v3. v3 is then negated and converts:
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; 0XFFFF -> 0
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; 0 -> 1
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; An optimized version is to follow this NFC patch
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define i32 @cols_needed(<4 x i16> %wide.load) {
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; POWERPC_64LE-LABEL: cols_needed:
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; POWERPC_64LE: # %bb.0: # %entry
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; POWERPC_64LE-NEXT: vspltish v3, 7
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; POWERPC_64LE-NEXT: li r3, 0
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; POWERPC_64LE-NEXT: vcmpequh v2, v2, v3
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; POWERPC_64LE-NEXT: vspltisw v3, 1
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; POWERPC_64LE-NEXT: xxlnor v2, v2, v2
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; POWERPC_64LE-NEXT: vmrglh v2, v2, v2
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; POWERPC_64LE-NEXT: xxland v2, v2, v3
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; POWERPC_64LE-NEXT: xxswapd v3, v2
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; POWERPC_64LE-NEXT: vadduwm v2, v2, v3
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; POWERPC_64LE-NEXT: xxspltw v3, v2, 2
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; POWERPC_64LE-NEXT: vadduwm v2, v2, v3
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; POWERPC_64LE-NEXT: vextuwrx r3, r3, v2
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; POWERPC_64LE-NEXT: blr
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;
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; POWERPC_64-LABEL: cols_needed:
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; POWERPC_64: # %bb.0: # %entry
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; POWERPC_64-NEXT: vspltish v3, 7
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; POWERPC_64-NEXT: li r3, 0
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; POWERPC_64-NEXT: vcmpequh v2, v2, v3
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; POWERPC_64-NEXT: vspltisw v3, 1
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; POWERPC_64-NEXT: xxlnor v2, v2, v2
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; POWERPC_64-NEXT: vmrghh v2, v2, v2
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; POWERPC_64-NEXT: xxland v2, v2, v3
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; POWERPC_64-NEXT: xxswapd v3, v2
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; POWERPC_64-NEXT: vadduwm v2, v2, v3
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; POWERPC_64-NEXT: xxspltw v3, v2, 1
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; POWERPC_64-NEXT: vadduwm v2, v2, v3
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; POWERPC_64-NEXT: vextuwlx r3, r3, v2
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; POWERPC_64-NEXT: blr
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;
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; POWERPC_32-LABEL: cols_needed:
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; POWERPC_32: # %bb.0: # %entry
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; POWERPC_32-NEXT: vspltish v3, 7
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; POWERPC_32-NEXT: vcmpequh v2, v2, v3
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; POWERPC_32-NEXT: vspltisw v3, 1
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; POWERPC_32-NEXT: xxlnor v2, v2, v2
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; POWERPC_32-NEXT: vmrghh v2, v2, v2
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; POWERPC_32-NEXT: xxland v2, v2, v3
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; POWERPC_32-NEXT: xxswapd v3, v2
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; POWERPC_32-NEXT: vadduwm v2, v2, v3
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; POWERPC_32-NEXT: xxspltw v3, v2, 1
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; POWERPC_32-NEXT: vadduwm v2, v2, v3
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; POWERPC_32-NEXT: stxv v2, -16(r1)
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; POWERPC_32-NEXT: lwz r3, -16(r1)
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; POWERPC_32-NEXT: blr
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entry:
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%0 = icmp ne <4 x i16> %wide.load, splat (i16 7)
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%1 = zext <4 x i1> %0 to <4 x i32>
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%2 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
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ret i32 %2
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #0
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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