531fd45e92
Currently it is considered suitable to lower to a bit test for a set of switch case clusters when the the number of unique destinations (`NumDests`) and the number of total comparisons (`NumCmps`) satisfy: `(NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) || (NumDests == 3 && NumCmps >= 6)` However it is found for some cases on powerpc, for example, when NumDests is 3, and the number of comparisons for each destination is all 2, it's not profitable to lower the switch to bit test. This is to add an option to set the minimum of largest number of comparisons to use bit test for switch lowering. --------- Co-authored-by: Shimin Cui <scui@xlperflep9.rtp.raleigh.ibm.com>
194 lines
5.9 KiB
LLVM
194 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs < %s -O3 -mcpu=ppc -mtriple powerpc-ibm-aix \
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; RUN: -ppc-asm-full-reg-names | FileCheck %s
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define i32 @foo(i32 noundef signext %x) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stwu r1, -64(r1)
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; CHECK-NEXT: stw r0, 72(r1)
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; CHECK-NEXT: cmpwi r3, 8
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; CHECK-NEXT: stw r31, 60(r1) # 4-byte Folded Spill
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; CHECK-NEXT: mr r31, r3
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: ble cr0, L..BB0_4
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: cmpwi r31, 11
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; CHECK-NEXT: bge cr0, L..BB0_7
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; CHECK-NEXT: # %bb.2: # %entry
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; CHECK-NEXT: cmplwi r31, 9
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; CHECK-NEXT: beq cr0, L..BB0_9
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; CHECK-NEXT: # %bb.3: # %entry
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; CHECK-NEXT: cmplwi r31, 10
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; CHECK-NEXT: beq cr0, L..BB0_11
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; CHECK-NEXT: b L..BB0_13
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; CHECK-NEXT: L..BB0_4: # %entry
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; CHECK-NEXT: cmplwi r31, 4
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; CHECK-NEXT: beq cr0, L..BB0_12
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; CHECK-NEXT: # %bb.5: # %entry
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; CHECK-NEXT: cmplwi r31, 7
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; CHECK-NEXT: beq cr0, L..BB0_11
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; CHECK-NEXT: # %bb.6: # %entry
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; CHECK-NEXT: cmplwi r31, 8
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; CHECK-NEXT: beq cr0, L..BB0_10
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; CHECK-NEXT: b L..BB0_13
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; CHECK-NEXT: L..BB0_7: # %entry
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; CHECK-NEXT: beq cr0, L..BB0_10
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; CHECK-NEXT: # %bb.8: # %entry
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; CHECK-NEXT: cmplwi r31, 12
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; CHECK-NEXT: bne cr0, L..BB0_13
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; CHECK-NEXT: L..BB0_9: # %sw.bb2
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: bl .foo3[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: b L..BB0_13
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; CHECK-NEXT: L..BB0_10: # %sw.bb1
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: bl .foo2[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: b L..BB0_13
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; CHECK-NEXT: L..BB0_11: # %sw.bb
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: bl .foo1[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: b L..BB0_13
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; CHECK-NEXT: L..BB0_12: # %sw.bb3
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: bl .foo4[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: L..BB0_13: # %return
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; CHECK-NEXT: lwz r31, 60(r1) # 4-byte Folded Reload
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; CHECK-NEXT: addi r1, r1, 64
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; CHECK-NEXT: lwz r0, 8(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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switch i32 %x, label %return [
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i32 7, label %sw.bb
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i32 10, label %sw.bb
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i32 8, label %sw.bb1
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i32 11, label %sw.bb1
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i32 9, label %sw.bb2
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i32 12, label %sw.bb2
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i32 4, label %sw.bb3
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]
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sw.bb: ; preds = %entry, %entry
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tail call void @foo1(i32 noundef signext %x)
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br label %return
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sw.bb1: ; preds = %entry, %entry
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tail call void @foo2(i32 noundef signext %x)
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br label %return
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sw.bb2: ; preds = %entry, %entry
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tail call void @foo3(i32 noundef signext %x)
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br label %return
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sw.bb3: ; preds = %entry
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tail call void @foo4(i32 noundef signext 4)
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br label %return
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return: ; preds = %sw.bb, %sw.bb1, %sw.bb2, %sw.bb3, %entry
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%retval.0 = phi i32 [ 0, %entry ], [ 4, %sw.bb3 ], [ %x, %sw.bb2 ], [ %x, %sw.bb1 ], [ %x, %sw.bb ]
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ret i32 %retval.0
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}
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define i32 @goo(i32 noundef signext %x) {
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; CHECK-LABEL: goo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stwu r1, -64(r1)
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; CHECK-NEXT: stw r0, 72(r1)
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; CHECK-NEXT: cmplwi r3, 12
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; CHECK-NEXT: stw r31, 60(r1) # 4-byte Folded Spill
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; CHECK-NEXT: mr r31, r3
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; CHECK-NEXT: bgt cr0, L..BB1_7
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: slw r3, r3, r31
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; CHECK-NEXT: andi. r4, r3, 5632
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; CHECK-NEXT: bne cr0, L..BB1_4
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; CHECK-NEXT: # %bb.2: # %entry
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; CHECK-NEXT: andi. r3, r3, 2304
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; CHECK-NEXT: beq cr0, L..BB1_5
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; CHECK-NEXT: # %bb.3: # %sw.bb1
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: bl .foo2[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: b L..BB1_9
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; CHECK-NEXT: L..BB1_4: # %sw.bb2
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: bl .foo3[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: b L..BB1_9
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; CHECK-NEXT: L..BB1_5: # %entry
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; CHECK-NEXT: cmplwi r31, 7
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; CHECK-NEXT: bne cr0, L..BB1_7
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; CHECK-NEXT: # %bb.6: # %sw.bb
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; CHECK-NEXT: li r3, 7
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; CHECK-NEXT: li r31, 7
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; CHECK-NEXT: bl .foo1[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: b L..BB1_9
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; CHECK-NEXT: L..BB1_7: # %entry
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; CHECK-NEXT: cmplwi r31, 4
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; CHECK-NEXT: li r31, 0
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; CHECK-NEXT: bne cr0, L..BB1_9
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; CHECK-NEXT: # %bb.8: # %sw.bb3
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: li r31, 4
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; CHECK-NEXT: bl .foo4[PR]
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; CHECK-NEXT: nop
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; CHECK-NEXT: L..BB1_9: # %return
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; CHECK-NEXT: mr r3, r31
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; CHECK-NEXT: lwz r31, 60(r1) # 4-byte Folded Reload
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; CHECK-NEXT: addi r1, r1, 64
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; CHECK-NEXT: lwz r0, 8(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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switch i32 %x, label %return [
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i32 7, label %sw.bb
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i32 8, label %sw.bb1
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i32 11, label %sw.bb1
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i32 9, label %sw.bb2
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i32 10, label %sw.bb2
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i32 12, label %sw.bb2
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i32 4, label %sw.bb3
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]
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sw.bb: ; preds = %entry
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tail call void @foo1(i32 noundef signext 7)
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br label %return
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sw.bb1: ; preds = %entry, %entry
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tail call void @foo2(i32 noundef signext %x)
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br label %return
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sw.bb2: ; preds = %entry, %entry, %entry
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tail call void @foo3(i32 noundef signext %x)
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br label %return
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sw.bb3: ; preds = %entry
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tail call void @foo4(i32 noundef signext 4)
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br label %return
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return: ; preds = %sw.bb, %sw.bb1, %sw.bb2, %sw.bb3, %entry
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%retval.0 = phi i32 [ 0, %entry ], [ 4, %sw.bb3 ], [ %x, %sw.bb2 ], [ %x, %sw.bb1 ], [ 7, %sw.bb ]
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ret i32 %retval.0
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}
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declare void @foo1(i32 noundef signext)
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declare void @foo2(i32 noundef signext)
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declare void @foo3(i32 noundef signext)
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declare void @foo4(i32 noundef signext)
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