a910a6a8b5
When computing the number of registers required by entry functions, the `AMDGPUAsmPrinter` needs to take into account both the register usage computed by the `AMDGPUResourceUsageAnalysis` pass, and the number of registers initialized by the hardware. At the moment, the way it computes the latter is different for graphics vs compute, due to differences in the implementation. For kernels, all the information needed is available in the `SIMachineFunctionInfo`, but for graphics shaders we would iterate over the `Function` arguments in the `AMDGPUAsmPrinter`. This pretty much repeats some of the logic from instruction selection. This patch introduces 2 new members to `SIMachineFunctionInfo`, one for SGPRs and one for VGPRs. Both will be computed during instruction selection and then used during `AMDGPUAsmPrinter`, removing the need to refer to the `Function` when printing assembly. This patch is NFC except for the fact that we now add the extra SGPRs (VCC, XNACK etc) to the number of SGPRs computed for graphics entry points. I'm not sure why these weren't included before. It would be nice if someone could confirm if that was just an oversight or if we have some docs somewhere that I haven't managed to find. Only one test is affected (its SGPR usage increases because we now take into account the XNACK registers).
39 lines
2.1 KiB
LLVM
39 lines
2.1 KiB
LLVM
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
|
|
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
|
|
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
|
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
|
|
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
|
|
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
|
|
|
; This compute shader has input args that claim that it has 17 sgprs and 5 vgprs
|
|
; in wave dispatch. Ensure that the sgpr and vgpr counts in COMPUTE_PGM_RSRC1
|
|
; are set to reflect that, even though the registers are not used in the shader.
|
|
|
|
; GCN-LABEL: {{^}}_amdgpu_cs_main:
|
|
; GCN: .amdgpu_pal_metadata
|
|
; GCN-NEXT: ---
|
|
; GCN-NEXT: amdpal.pipelines:
|
|
; GCN-NEXT: - .hardware_stages:
|
|
; GCN-NEXT: .cs:
|
|
; GCN-NEXT: .entry_point: _amdgpu_cs_main
|
|
; GCN-NEXT: .entry_point_symbol: _amdgpu_cs_main
|
|
; GCN-NEXT: .scratch_memory_size: 0
|
|
; SI-NEXT: .sgpr_count: 0x11
|
|
; VI-NEXT: .sgpr_count: 0x60
|
|
; GFX9-NEXT: .sgpr_count: 0x15
|
|
; SI-NEXT: .vgpr_count: 0x5
|
|
; VI-NEXT: .vgpr_count: 0x5
|
|
; GFX9-NEXT: .vgpr_count: 0x5
|
|
; GCN-NEXT: .registers:
|
|
; SI-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}81
|
|
; VI-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}c1
|
|
; GFX9-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}81
|
|
; GCN-NEXT: '0x2e13 (COMPUTE_PGM_RSRC2)': 0
|
|
; GCN-NEXT: ...
|
|
; GCN-NEXT: .end_amdgpu_pal_metadata
|
|
|
|
define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg, i32 inreg, <2 x i32> inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <5 x i32>) {
|
|
.entry:
|
|
ret void
|
|
}
|