cba7dcd107
Add rules for G_AMDGPU_BUFFER_STORE, G_AMDGPU_BUFFER_STORE_FORMAT, G_AMDGPU_BUFFER_STORE_FORMAT_D16, and G_AMDGPU_TBUFFER_STORE_FORMAT.
103 lines
4.1 KiB
LLVM
103 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GISEL %s
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; Check that in strict OOB mode for buffers (relaxed-buffer-oob-mode attribute not set) the underaligned loads and stores get split.
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; FIXME: The loads/stores do not get split (extend amdgpu-lower-buffer-fat-pointers?).
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define amdgpu_ps void @split_underaligned_load(ptr addrspace(7) inreg %p, ptr addrspace(7) inreg %p2) #0 {
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; CHECK-LABEL: split_underaligned_load:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: v_mov_b32_e32 v2, s9
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; CHECK-NEXT: s_mov_b32 s15, s8
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; CHECK-NEXT: s_mov_b32 s14, s7
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; CHECK-NEXT: s_mov_b32 s13, s6
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; CHECK-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
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; CHECK-NEXT: s_mov_b32 s12, s5
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_store_b64 v[0:1], v2, s[12:15], 0 offen
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; CHECK-NEXT: s_endpgm
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; SDAG-LABEL: split_underaligned_load:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: v_mov_b32_e32 v0, s4
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; SDAG-NEXT: v_mov_b32_e32 v2, s9
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; SDAG-NEXT: s_mov_b32 s15, s8
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; SDAG-NEXT: s_mov_b32 s14, s7
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; SDAG-NEXT: s_mov_b32 s13, s6
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; SDAG-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
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; SDAG-NEXT: s_mov_b32 s12, s5
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: buffer_store_b64 v[0:1], v2, s[12:15], 0 offen
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: split_underaligned_load:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: v_mov_b32_e32 v0, s4
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; GISEL-NEXT: v_mov_b32_e32 v2, s9
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; GISEL-NEXT: s_mov_b32 s12, s5
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; GISEL-NEXT: s_mov_b32 s13, s6
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; GISEL-NEXT: s_mov_b32 s14, s7
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; GISEL-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
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; GISEL-NEXT: s_mov_b32 s15, s8
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: buffer_store_b64 v[0:1], v2, s[12:15], 0 offen
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; GISEL-NEXT: s_endpgm
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entry:
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%gep = getelementptr i8, ptr addrspace(7) %p, i32 0
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%ld = load i64, ptr addrspace(7) %gep, align 4
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%gep2 = getelementptr i8, ptr addrspace(7) %p2, i32 0
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store i64 %ld, ptr addrspace(7) %gep2, align 4
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ret void
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}
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; Check that in strict OOB mode for buffers (relaxed-buffer-oob-mode attribute not set) the naturally aligned loads and stores do not get split.
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define amdgpu_ps void @do_not_split_aligned_load(ptr addrspace(7) inreg %p, ptr addrspace(7) inreg %p2) #0 {
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; CHECK-LABEL: do_not_split_aligned_load:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: v_mov_b32_e32 v2, s9
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; CHECK-NEXT: s_mov_b32 s15, s8
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; CHECK-NEXT: s_mov_b32 s14, s7
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; CHECK-NEXT: s_mov_b32 s13, s6
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; CHECK-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
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; CHECK-NEXT: s_mov_b32 s12, s5
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_store_b64 v[0:1], v2, s[12:15], 0 offen
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; CHECK-NEXT: s_endpgm
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; SDAG-LABEL: do_not_split_aligned_load:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: v_mov_b32_e32 v0, s4
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; SDAG-NEXT: v_mov_b32_e32 v2, s9
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; SDAG-NEXT: s_mov_b32 s15, s8
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; SDAG-NEXT: s_mov_b32 s14, s7
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; SDAG-NEXT: s_mov_b32 s13, s6
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; SDAG-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
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; SDAG-NEXT: s_mov_b32 s12, s5
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: buffer_store_b64 v[0:1], v2, s[12:15], 0 offen
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: do_not_split_aligned_load:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: v_mov_b32_e32 v0, s4
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; GISEL-NEXT: v_mov_b32_e32 v2, s9
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; GISEL-NEXT: s_mov_b32 s12, s5
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; GISEL-NEXT: s_mov_b32 s13, s6
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; GISEL-NEXT: s_mov_b32 s14, s7
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; GISEL-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
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; GISEL-NEXT: s_mov_b32 s15, s8
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: buffer_store_b64 v[0:1], v2, s[12:15], 0 offen
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; GISEL-NEXT: s_endpgm
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entry:
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%gep = getelementptr i8, ptr addrspace(7) %p, i32 0
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%ld = load i64, ptr addrspace(7) %gep, align 8
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%gep2 = getelementptr i8, ptr addrspace(7) %p2, i32 0
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store i64 %ld, ptr addrspace(7) %gep2, align 8
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ret void
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}
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