a97f5ec95f
Fix ABI on old subtargets so match new subtargets, packing 16-bit element subvectors into 32-bit registers. Previously this would be scalarized and promoted to i32/float. Note this only changes the vector cases. Scalar i16/half are still promoted to i32/float for now. I've unsuccessfully tried to make that switch in the past, so leave that for later. This will help with removal of softPromoteHalfType.
450 lines
18 KiB
LLVM
450 lines
18 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti | FileCheck %s -enable-var-scope -check-prefixes=GCN,SI
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; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji | FileCheck %s -enable-var-scope -check-prefixes=GCN,VI
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; Make sure high constant 0 isn't pointlessly materialized
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define i16 @trunc_bitcast_i64_lshr_32_i16(i64 %bar) {
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; GCN-LABEL: trunc_bitcast_i64_lshr_32_i16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%srl = lshr i64 %bar, 32
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%trunc = trunc i64 %srl to i16
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ret i16 %trunc
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}
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define i32 @trunc_bitcast_i64_lshr_32_i32(i64 %bar) {
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; GCN-LABEL: trunc_bitcast_i64_lshr_32_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%srl = lshr i64 %bar, 32
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%trunc = trunc i64 %srl to i32
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ret i32 %trunc
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}
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define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {
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; SI-LABEL: trunc_bitcast_v2i32_to_i16:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: trunc_bitcast_v2i32_to_i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: flat_load_dword v0, v[0:1]
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%load0 = load i32, ptr addrspace(1) poison
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%load1 = load i32, ptr addrspace(1) null
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%insert.0 = insertelement <2 x i32> poison, i32 %load0, i32 0
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%insert.1 = insertelement <2 x i32> %insert.0, i32 99, i32 1
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%bc = bitcast <2 x i32> %insert.1 to i64
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%trunc = trunc i64 %bc to i16
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%add = add i16 %trunc, 4
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ret i16 %add
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}
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; Make sure there's no crash if the source vector type is FP
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define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {
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; SI-LABEL: trunc_bitcast_v2f32_to_i16:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: trunc_bitcast_v2f32_to_i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: flat_load_dword v0, v[0:1]
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%load0 = load float, ptr addrspace(1) poison
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%load1 = load float, ptr addrspace(1) null
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%insert.0 = insertelement <2 x float> poison, float %load0, i32 0
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%insert.1 = insertelement <2 x float> %insert.0, float 4.0, i32 1
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%bc = bitcast <2 x float> %insert.1 to i64
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%trunc = trunc i64 %bc to i16
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%add = add i16 %trunc, 4
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ret i16 %add
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}
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define amdgpu_kernel void @truncate_high_elt_extract_vector(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture readonly %arg1, ptr addrspace(1) nocapture %arg2) local_unnamed_addr {
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; SI-LABEL: truncate_high_elt_extract_vector:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_load_dword s0, s[0:1], 0x0
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; SI-NEXT: s_load_dword s1, s[2:3], 0x0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_sext_i32_i16 s0, s0
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; SI-NEXT: s_sext_i32_i16 s1, s1
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; SI-NEXT: s_mul_i32 s1, s1, s0
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; SI-NEXT: s_lshr_b32 s0, s1, 16
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; SI-NEXT: v_mov_b32_e32 v0, s0
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: truncate_high_elt_extract_vector:
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; VI: ; %bb.0: ; %bb
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_load_dword s0, s[0:1], 0x0
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; VI-NEXT: s_load_dword s1, s[2:3], 0x0
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: v_mov_b32_e32 v1, s5
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_sext_i32_i16 s0, s0
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; VI-NEXT: s_sext_i32_i16 s1, s1
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; VI-NEXT: s_mul_i32 s1, s1, s0
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; VI-NEXT: s_lshr_b32 s0, s1, 16
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; VI-NEXT: v_mov_b32_e32 v2, s0
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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bb:
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%tmp = getelementptr inbounds <2 x i16>, ptr addrspace(1) %arg, i64 0
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%tmp3 = load <2 x i16>, ptr addrspace(1) %tmp, align 4
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%tmp4 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %arg1, i64 0
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%tmp5 = load <2 x i16>, ptr addrspace(1) %tmp4, align 4
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%tmp6 = sext <2 x i16> %tmp3 to <2 x i32>
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%tmp7 = sext <2 x i16> %tmp5 to <2 x i32>
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%tmp8 = extractelement <2 x i32> %tmp6, i64 0
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%tmp9 = extractelement <2 x i32> %tmp7, i64 0
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%tmp10 = mul nsw i32 %tmp9, %tmp8
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%tmp11 = insertelement <2 x i32> poison, i32 %tmp10, i32 0
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%tmp12 = insertelement <2 x i32> %tmp11, i32 poison, i32 1
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%tmp13 = lshr <2 x i32> %tmp12, <i32 16, i32 16>
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%tmp14 = trunc <2 x i32> %tmp13 to <2 x i16>
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%tmp15 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %arg2, i64 0
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store <2 x i16> %tmp14, ptr addrspace(1) %tmp15, align 4
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ret void
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}
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define <2 x i16> @trunc_v2i64_arg_to_v2i16(<2 x i64> %arg0) #0 {
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; SI-LABEL: trunc_v2i64_arg_to_v2i16:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: trunc_v2i64_arg_to_v2i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s4, 0x1000504
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; VI-NEXT: v_perm_b32 v0, v0, v2, s4
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; VI-NEXT: s_setpc_b64 s[30:31]
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%trunc = trunc <2 x i64> %arg0 to <2 x i16>
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ret <2 x i16> %trunc
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}
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; Test for regression where an unnecessary v_alignbit_b32 was inserted
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; on the final result, due to losing the fact that the upper half of
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; the lhs vector was undef.
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define <2 x i16> @vector_trunc_high_bits_undef_lshr_lhs_alignbit_regression(i32 %arg0) {
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; GCN-LABEL: vector_trunc_high_bits_undef_lshr_lhs_alignbit_regression:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = lshr <2 x i32> %undef.hi.elt, splat (i32 16)
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_lshr_rhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_lshr_rhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_lshr_b32_e32 v0, 16, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: vector_trunc_high_bits_undef_lshr_rhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_lshrrev_b32_e64 v0, v0, 16
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; VI-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = lshr <2 x i32> splat (i32 16), %undef.hi.elt
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_ashr_lhs_alignbit_regression(i32 %arg0) {
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; GCN-LABEL: vector_trunc_high_bits_undef_ashr_lhs_alignbit_regression:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%ashr = ashr <2 x i32> %undef.hi.elt, splat (i32 16)
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%trunc = trunc <2 x i32> %ashr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_ashr_rhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_ashr_rhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_ashr_i32_e32 v0, -4, v0
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: vector_trunc_high_bits_undef_ashr_rhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_ashrrev_i32_e64 v0, v0, -4
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; VI-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = ashr <2 x i32> splat (i32 -4), %undef.hi.elt
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_add_lhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_add_lhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_add_i32_e32 v0, vcc, 16, v0
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: vector_trunc_high_bits_undef_add_lhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_add_u32_e32 v0, vcc, 16, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = add <2 x i32> %undef.hi.elt, splat (i32 16)
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_shl_rhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_shl_rhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_lshl_b32_e32 v0, 2, v0
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; SI-NEXT: v_and_b32_e32 v0, 0xfffe, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: vector_trunc_high_bits_undef_shl_rhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_lshlrev_b32_e64 v0, v0, 2
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; VI-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = shl <2 x i32> splat (i32 2), %undef.hi.elt
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_sub_lhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_sub_lhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_add_i32_e32 v0, vcc, -16, v0
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: vector_trunc_high_bits_undef_sub_lhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = sub <2 x i32> %undef.hi.elt, splat (i32 16)
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_or_lhs_alignbit_regression(i32 %arg0) {
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; GCN-LABEL: vector_trunc_high_bits_undef_or_lhs_alignbit_regression:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_or_b32_e32 v0, 0xffff0011, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = or <2 x i32> %undef.hi.elt, splat (i32 17)
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_xor_lhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_xor_lhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_xor_b32_e32 v0, 17, v0
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: vector_trunc_high_bits_undef_xor_lhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_xor_b32_e32 v0, 17, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = xor <2 x i32> %undef.hi.elt, splat (i32 17)
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_shl_lhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_shl_lhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; SI-NEXT: v_and_b32_e32 v0, 0xfffc, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: vector_trunc_high_bits_undef_shl_lhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_lshlrev_b16_e32 v0, 2, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%shl = shl <2 x i32> %undef.hi.elt, splat (i32 2)
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%trunc = trunc <2 x i32> %shl to <2 x i16>
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ret <2 x i16> %trunc
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}
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define <2 x i16> @vector_trunc_high_bits_undef_mul_lhs_alignbit_regression(i32 %arg0) {
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; GCN-LABEL: vector_trunc_high_bits_undef_mul_lhs_alignbit_regression:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mul_lo_u32 v0, v0, 18
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; GCN-NEXT: v_and_b32_e32 v0, 0xfffe, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
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%lshr = mul <2 x i32> %undef.hi.elt, splat (i32 18)
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%trunc = trunc <2 x i32> %lshr to <2 x i16>
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ret <2 x i16> %trunc
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}
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|
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define <2 x i16> @vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression(i32 %arg0) {
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; SI-LABEL: vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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|
; SI-NEXT: s_mov_b32 s4, 0x38e38e39
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; SI-NEXT: v_mul_hi_i32 v0, v0, s4
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; SI-NEXT: v_lshrrev_b32_e32 v1, 31, v0
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|
; SI-NEXT: v_lshrrev_b32_e32 v0, 2, v0
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|
; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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|
; SI-NEXT: s_setpc_b64 s[30:31]
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|
;
|
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; VI-LABEL: vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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|
; VI-NEXT: s_mov_b32 s4, 0x38e38e39
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; VI-NEXT: v_mul_hi_i32 v0, v0, s4
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|
; VI-NEXT: v_lshrrev_b32_e32 v1, 31, v0
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; VI-NEXT: v_ashrrev_i32_e32 v0, 2, v0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
|
|
%lshr = sdiv <2 x i32> %undef.hi.elt, splat (i32 18)
|
|
%trunc = trunc <2 x i32> %lshr to <2 x i16>
|
|
ret <2 x i16> %trunc
|
|
}
|
|
|
|
define <2 x i16> @vector_trunc_high_bits_undef_srem_lhs_alignbit_regression(i32 %arg0) {
|
|
; SI-LABEL: vector_trunc_high_bits_undef_srem_lhs_alignbit_regression:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_mov_b32 s4, 0x38e38e39
|
|
; SI-NEXT: v_mul_hi_i32 v1, v0, s4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 31, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
|
|
; SI-NEXT: v_mul_lo_u32 v1, v1, 18
|
|
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: vector_trunc_high_bits_undef_srem_lhs_alignbit_regression:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_mov_b32 s4, 0x38e38e39
|
|
; VI-NEXT: v_mul_hi_i32 v1, v0, s4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 31, v1
|
|
; VI-NEXT: v_ashrrev_i32_e32 v1, 2, v1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
|
|
; VI-NEXT: v_mul_lo_u32 v1, v1, 18
|
|
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
|
|
%lshr = srem <2 x i32> %undef.hi.elt, splat (i32 18)
|
|
%trunc = trunc <2 x i32> %lshr to <2 x i16>
|
|
ret <2 x i16> %trunc
|
|
}
|
|
|
|
|
|
define <2 x i16> @vector_trunc_high_bits_undef_udiv_lhs_alignbit_regression(i32 %arg0) {
|
|
; SI-LABEL: vector_trunc_high_bits_undef_udiv_lhs_alignbit_regression:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_mov_b32 s4, 0x38e38e39
|
|
; SI-NEXT: v_mul_hi_u32 v0, v0, s4
|
|
; SI-NEXT: v_bfe_u32 v0, v0, 2, 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: vector_trunc_high_bits_undef_udiv_lhs_alignbit_regression:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_mov_b32 s4, 0x38e38e39
|
|
; VI-NEXT: v_mul_hi_u32 v0, v0, s4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v0, 2, v0
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
|
|
%lshr = udiv <2 x i32> %undef.hi.elt, splat (i32 18)
|
|
%trunc = trunc <2 x i32> %lshr to <2 x i16>
|
|
ret <2 x i16> %trunc
|
|
}
|
|
|
|
define <2 x i16> @vector_trunc_high_bits_undef_urem_lhs_alignbit_regression(i32 %arg0) {
|
|
; SI-LABEL: vector_trunc_high_bits_undef_urem_lhs_alignbit_regression:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_mov_b32 s4, 0x38e38e39
|
|
; SI-NEXT: v_mul_hi_u32 v1, v0, s4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1
|
|
; SI-NEXT: v_mul_lo_u32 v1, v1, 18
|
|
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: vector_trunc_high_bits_undef_urem_lhs_alignbit_regression:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_mov_b32 s4, 0x38e38e39
|
|
; VI-NEXT: v_mul_hi_u32 v1, v0, s4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 2, v1
|
|
; VI-NEXT: v_mul_lo_u32 v1, v1, 18
|
|
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
|
|
%lshr = urem <2 x i32> %undef.hi.elt, splat (i32 18)
|
|
%trunc = trunc <2 x i32> %lshr to <2 x i16>
|
|
ret <2 x i16> %trunc
|
|
}
|